X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=board%2Ffreescale%2Ft104xrdb%2Fddr.c;h=2b1b28da8856d3f266a28838468533144b263ab0;hb=83d290c56fab2d38cd1ab4c4cc7099559c1d5046;hp=e1148e568e8ee66a9ae36adf0764083a81621a84;hpb=b79dadf846e5e140e261bbfa4decd024357702d7;p=platform%2Fkernel%2Fu-boot.git diff --git a/board/freescale/t104xrdb/ddr.c b/board/freescale/t104xrdb/ddr.c index e1148e5..2b1b28d 100644 --- a/board/freescale/t104xrdb/ddr.c +++ b/board/freescale/t104xrdb/ddr.c @@ -1,7 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2013 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -75,7 +74,13 @@ found: * Factors to consider for half-strength driver enable: * - number of DIMMs installed */ +#ifdef CONFIG_SYS_FSL_DDR4 + popts->half_strength_driver_enable = 1; + /* optimize cpo for erratum A-009942 */ + popts->cpo_sample = 0x59; +#else popts->half_strength_driver_enable = 0; +#endif /* * Write leveling override */ @@ -91,8 +96,14 @@ found: popts->zq_en = 1; /* DHC_EN =1, ODT = 75 Ohm */ +#ifdef CONFIG_SYS_FSL_DDR4 + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_120OHM); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_120OHM) | + DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */ +#else popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); +#endif } #if defined(CONFIG_DEEP_SLEEP) @@ -108,25 +119,24 @@ void board_mem_sleep_setup(void) } #endif -phys_size_t initdram(int board_type) +int dram_init(void) { phys_size_t dram_size; #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) puts("Initializing....using SPD\n"); - dram_size = fsl_ddr_sdram(); - - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - #else dram_size = fsl_ddr_sdram_size(); #endif + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD) fsl_dp_resume(); #endif - return dram_size; + gd->ram_size = dram_size; + + return 0; }