X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=board%2Ffreescale%2Fp2041rdb%2Fp2041rdb.c;h=1b1263091e50e550f07169e1d262205a08687032;hb=6cc04547cb3bbd3a3d78947f200acbae19e3c67f;hp=8554512df69eabea0ff8fe6b35bb2d1f80687a54;hpb=85b8c5c4bf80025de4632ae6c9a8a606e51508a4;p=platform%2Fkernel%2Fu-boot.git diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c index 8554512..1b12630 100644 --- a/board/freescale/p2041rdb/p2041rdb.c +++ b/board/freescale/p2041rdb/p2041rdb.c @@ -1,12 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2011,2012 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ */ #include +#include #include +#include +#include +#include +#include #include +#include #include #include #include @@ -14,11 +19,10 @@ #include #include #include -#include #include #include -extern void pci_of_setup(void *blob, bd_t *bd); +extern void pci_of_setup(void *blob, struct bd_info *bd); #include "cpld.h" @@ -62,7 +66,7 @@ int checkboard(void) int board_early_init_f(void) { - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); /* board only uses the DDR_MCK0/1, so disable the DDR_MCK2/3 */ setbits_be32(&gur->ddrclkdr, 0x000f000f); @@ -77,7 +81,7 @@ int board_early_init_f(void) void board_config_lanes_mux(void) { - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; int srds_prtcl = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; @@ -116,7 +120,7 @@ void board_config_lanes_mux(void) int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + int flash_esel = find_tlb_idx((void *)flashbase, 1); /* * Remap Boot flash + PROMJET region to caching-inhibited @@ -127,21 +131,25 @@ int board_early_init_r(void) flush_dcache(); invalidate_icache(); - /* invalidate existing TLB entry for flash + promjet */ - disable_tlb(flash_esel); + if (flash_esel == -1) { + /* very unlikely unless something is messed up */ + puts("Error: Could not find TLB for FLASH BASE\n"); + flash_esel = 2; /* give our best effort to continue */ + } else { + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + } set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1); - set_liodns(); - setup_portals(); board_config_lanes_mux(); return 0; } -unsigned long get_board_sys_clk(unsigned long dummy) +unsigned long get_board_sys_clk(void) { u8 sysclk_conf = CPLD_READ(sysclk_sw1); @@ -159,7 +167,7 @@ unsigned long get_board_sys_clk(unsigned long dummy) int misc_init_r(void) { - serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + serdes_corenet_t *regs = (void *)CFG_SYS_FSL_CORENET_SERDES_ADDR; u32 actual[NUM_SRDS_BANKS]; unsigned int i; u8 sw; @@ -209,20 +217,20 @@ int misc_init_r(void) return 0; } -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, struct bd_info *bd) { phys_addr_t base; phys_size_t size; ft_cpu_setup(blob, bd); - base = getenv_bootm_low(); - size = getenv_bootm_size(); + base = env_get_bootm_low(); + size = env_get_bootm_size(); fdt_fixup_memory(blob, (u64)base, (u64)size); -#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) - fdt_fixup_dr_usb(blob, bd); +#if defined(CONFIG_HAS_FSL_DR_USB) + fsl_fdt_fixup_dr_usb(blob, bd); #endif #ifdef CONFIG_PCI @@ -231,6 +239,10 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_liodn(blob); #ifdef CONFIG_SYS_DPAA_FMAN +#ifndef CONFIG_DM_ETH fdt_fixup_fman_ethernet(blob); #endif +#endif + + return 0; }