X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=board%2Ffreescale%2Fmpc8610hpcd%2Fmpc8610hpcd.c;h=f42c3167224d5f843476b81b00554fc42760538b;hb=06f43286c6354aaab0103615e83893512f86eee7;hp=dacd2a911fe2829787c964b7243b46992f529381;hpb=d35c451d6cff3e77e40fbdfc7a2933cdcb86ae4b;p=platform%2Fkernel%2Fu-boot.git diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c index dacd2a9..f42c316 100644 --- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c +++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c @@ -25,7 +25,7 @@ #include #include #include -#include +#include #include #include #include @@ -36,12 +36,8 @@ #include "../common/pixis.h" -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) -extern void ddr_enable_ecc(unsigned int dram_size); -#endif - void sdram_init(void); -long int fixed_sdram(void); +phys_size_t fixed_sdram(void); void mpc8610hpcd_diu_init(void); @@ -59,16 +55,17 @@ int board_early_init_f(void) int misc_init_r(void) { u8 tmp_val, version; + u8 *pixis_base = (u8 *)PIXIS_BASE; /*Do not use 8259PIC*/ - tmp_val = in8(PIXIS_BASE + PIXIS_BRDCFG0); - out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val | 0x80); + tmp_val = in_8(pixis_base + PIXIS_BRDCFG0); + out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x80); /*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/ - version = in8(PIXIS_BASE + PIXIS_PVER); + version = in_8(pixis_base + PIXIS_PVER); if(version >= 0x07) { - tmp_val = in8(PIXIS_BASE + PIXIS_BRDCFG0); - out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val & 0xbf); + tmp_val = in_8(pixis_base + PIXIS_BRDCFG0); + out_8(pixis_base + PIXIS_BRDCFG0, tmp_val & 0xbf); } /* Using this for DIU init before the driver in linux takes over @@ -100,11 +97,12 @@ int checkboard(void) { volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm; + u8 *pixis_base = (u8 *)PIXIS_BASE; printf ("Board: MPC8610HPCD, System ID: 0x%02x, " "System Version: 0x%02x, FPGA Version: 0x%02x\n", - in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER), - in8(PIXIS_BASE + PIXIS_PVER)); + in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), + in_8(pixis_base + PIXIS_PVER)); mcm->abcr |= 0x00010000; /* 0 */ mcm->hpmr3 = 0x80000008; /* 4c */ @@ -121,7 +119,7 @@ int checkboard(void) phys_size_t initdram(int board_type) { - long dram_size = 0; + phys_size_t dram_size = 0; #if defined(CONFIG_SPD_EEPROM) dram_size = fsl_ddr_sdram(); @@ -129,18 +127,6 @@ initdram(int board_type) dram_size = fixed_sdram(); #endif -#if defined(CONFIG_SYS_RAMBOOT) - puts(" DDR: "); - return dram_size; -#endif - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - /* - * Initialize and enable DDR ECC. - */ - ddr_enable_ecc(dram_size); -#endif - puts(" DDR: "); return dram_size; } @@ -151,7 +137,7 @@ initdram(int board_type) * Fixed sdram init -- doesn't use serial presence detect. */ -long int fixed_sdram(void) +phys_size_t fixed_sdram(void) { #if !defined(CONFIG_SYS_RAMBOOT) volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; @@ -165,7 +151,7 @@ long int fixed_sdram(void) ddr->timing_cfg_0 = 0x00260802; ddr->timing_cfg_1 = 0x3935d322; ddr->timing_cfg_2 = 0x14904cc8; - ddr->sdram_mode_1 = 0x00480432; + ddr->sdram_mode = 0x00480432; ddr->sdram_mode_2 = 0x00000000; ddr->sdram_interval = 0x06180fff; /* 0x06180100; */ ddr->sdram_data_init = 0xDEADBEEF; @@ -181,7 +167,7 @@ long int fixed_sdram(void) udelay(500); - ddr->sdram_cfg_1 = 0xc3000000; /* 0xe3008000;*/ + ddr->sdram_cfg = 0xc3000000; /* 0xe3008000;*/ #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) @@ -240,9 +226,6 @@ static struct pci_controller pcie2_hose; int first_free_busno = 0; -extern int fsl_pci_setup_inbound_windows(struct pci_region *r); -extern void fsl_pci_init(struct pci_controller *hose); - void pci_init_board(void) { volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; @@ -260,9 +243,8 @@ void pci_init_board(void) { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; struct pci_controller *hose = &pcie1_hose; - int pcie_configured = (io_sel == 1) || (io_sel == 4); - int pcie_ep = (host_agent == 0) || (host_agent == 2) || - (host_agent == 5); + int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); + int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); struct pci_region *r = hose->regions; if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)) { @@ -272,19 +254,16 @@ void pci_init_board(void) if (pci->pme_msg_det) pci->pme_msg_det = 0xffffffff; - /* inbound */ - r += fsl_pci_setup_inbound_windows(r); - /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCIE1_MEM_BASE, + CONFIG_SYS_PCIE1_MEM_BUS, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ pci_set_region(r++, - CONFIG_SYS_PCIE1_IO_BASE, + CONFIG_SYS_PCIE1_IO_BUS, CONFIG_SYS_PCIE1_IO_PHYS, CONFIG_SYS_PCIE1_IO_SIZE, PCI_REGION_IO); @@ -292,10 +271,8 @@ void pci_init_board(void) hose->region_count = r - hose->regions; hose->first_busno = first_free_busno; - pci_setup_indirect(hose, (int)&pci->cfg_addr, - (int)&pci->cfg_data); - fsl_pci_init(hose); + fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); first_free_busno = hose->last_busno + 1; printf(" PCI-Express 1 on bus %02x - %02x\n", @@ -315,9 +292,8 @@ void pci_init_board(void) struct pci_controller *hose = &pcie2_hose; struct pci_region *r = hose->regions; - int pcie_configured = (io_sel == 0) || (io_sel == 4); - int pcie_ep = (host_agent == 0) || (host_agent == 1) || - (host_agent == 4); + int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); + int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent); if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE2)) { printf(" PCI-Express 2 connected to slot as %s" \ @@ -327,19 +303,16 @@ void pci_init_board(void) if (pci->pme_msg_det) pci->pme_msg_det = 0xffffffff; - /* inbound */ - r += fsl_pci_setup_inbound_windows(r); - /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCIE2_MEM_BASE, + CONFIG_SYS_PCIE2_MEM_BUS, CONFIG_SYS_PCIE2_MEM_PHYS, CONFIG_SYS_PCIE2_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ pci_set_region(r++, - CONFIG_SYS_PCIE2_IO_BASE, + CONFIG_SYS_PCIE2_IO_BUS, CONFIG_SYS_PCIE2_IO_PHYS, CONFIG_SYS_PCIE2_IO_SIZE, PCI_REGION_IO); @@ -347,10 +320,8 @@ void pci_init_board(void) hose->region_count = r - hose->regions; hose->first_busno = first_free_busno; - pci_setup_indirect(hose, (int)&pci->cfg_addr, - (int)&pci->cfg_data); - fsl_pci_init(hose); + fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); first_free_busno = hose->last_busno + 1; printf(" PCI-Express 2 on bus %02x - %02x\n", @@ -367,7 +338,7 @@ void pci_init_board(void) { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; struct pci_controller *hose = &pci1_hose; - int pci_agent = (host_agent >= 4) && (host_agent <= 6); + int pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI_1, host_agent); struct pci_region *r = hose->regions; if ( !(devdisr & MPC86xx_DEVDISR_PCI1)) { @@ -376,19 +347,16 @@ void pci_init_board(void) pci_agent ? "Agent" : "Host", (uint)pci); - /* inbound */ - r += fsl_pci_setup_inbound_windows(r); - /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCI1_MEM_BASE, + CONFIG_SYS_PCI1_MEM_BUS, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ pci_set_region(r++, - CONFIG_SYS_PCI1_IO_BASE, + CONFIG_SYS_PCI1_IO_BUS, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); @@ -396,10 +364,8 @@ void pci_init_board(void) hose->region_count = r - hose->regions; hose->first_busno = first_free_busno; - pci_setup_indirect(hose, (int) &pci->cfg_addr, - (int) &pci->cfg_data); - fsl_pci_init(hose); + fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); first_free_busno = hose->last_busno + 1; printf(" PCI on bus %02x - %02x\n", @@ -413,25 +379,10 @@ void pci_init_board(void) } #if defined(CONFIG_OF_BOARD_SETUP) -extern void ft_fsl_pci_setup(void *blob, const char *pci_alias, - struct pci_controller *hose); - void ft_board_setup(void *blob, bd_t *bd) { - do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, - "timebase-frequency", bd->bi_busfreq / 4, 1); - do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, - "bus-frequency", bd->bi_busfreq, 1); - do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, - "clock-frequency", bd->bi_intfreq, 1); - do_fixup_by_prop_u32(blob, "device_type", "soc", 4, - "bus-frequency", bd->bi_busfreq, 1); - - do_fixup_by_compat_u32(blob, "ns16550", - "clock-frequency", bd->bi_busfreq, 1); - - fdt_fixup_memory(blob, bd->bi_memstart, bd->bi_memsize); + ft_cpu_setup(blob, bd); #ifdef CONFIG_PCI1 ft_fsl_pci_setup(blob, "pci0", &pci1_hose); @@ -455,10 +406,9 @@ get_board_sys_clk(ulong dummy) { u8 i; ulong val = 0; - ulong a; + u8 *pixis_base = (u8 *)PIXIS_BASE; - a = PIXIS_BASE + PIXIS_SPD; - i = in8(a); + i = in_8(pixis_base + PIXIS_SPD); i &= 0x07; switch (i) { @@ -495,3 +445,13 @@ int board_eth_init(bd_t *bis) { return pci_eth_init(bis); } + +void board_reset(void) +{ + u8 *pixis_base = (u8 *)PIXIS_BASE; + + out_8(pixis_base + PIXIS_RST, 0); + + while (1) + ; +}