X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=board%2Ffreescale%2Fmpc8569mds%2Fbcsr.c;h=178d9f873d6ba0de2d54d36e34f0bc3cf6d7bda4;hb=3765b3e7bd0f8e46914d417f29cbcb0c72b1acf7;hp=17c8478a628a89b9b9b0fd9691a90e9ba1858398;hpb=750098d33bc362ac4263863e92da158cf011063f;p=platform%2Fkernel%2Fu-boot.git

diff --git a/board/freescale/mpc8569mds/bcsr.c b/board/freescale/mpc8569mds/bcsr.c
index 17c8478..178d9f8 100644
--- a/board/freescale/mpc8569mds/bcsr.c
+++ b/board/freescale/mpc8569mds/bcsr.c
@@ -1,23 +1,7 @@
 /*
- * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
+ * Copyright (C) 2009 Freescale Semiconductor, Inc.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
@@ -25,18 +9,19 @@
 
 #include "bcsr.h"
 
-void enable_8569mds_flash_write()
+void enable_8569mds_flash_write(void)
 {
 	setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP);
 }
 
-void disable_8569mds_flash_write()
+void disable_8569mds_flash_write(void)
 {
 	clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP);
 }
 
-void enable_8569mds_qe_mdio()
+void enable_8569mds_qe_uec(void)
 {
+#if defined(CONFIG_SYS_UCC_RGMII_MODE)
 	setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7),
 			BCSR7_UCC1_GETH_EN | BCSR7_UCC1_RGMII_EN);
 	setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 8),
@@ -45,9 +30,21 @@ void enable_8569mds_qe_mdio()
 			BCSR9_UCC3_GETH_EN | BCSR9_UCC3_RGMII_EN);
 	setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 10),
 			BCSR10_UCC4_GETH_EN | BCSR10_UCC4_RGMII_EN);
+#elif defined(CONFIG_SYS_UCC_RMII_MODE)
+	/* Set UCC1-4 working at RMII mode */
+	clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7),
+			BCSR7_UCC1_GETH_EN | BCSR7_UCC1_RGMII_EN);
+	clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 8),
+			BCSR8_UCC2_GETH_EN | BCSR8_UCC2_RGMII_EN);
+	clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9),
+			BCSR9_UCC3_GETH_EN | BCSR9_UCC3_RGMII_EN);
+	clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 10),
+			BCSR10_UCC4_GETH_EN | BCSR10_UCC4_RGMII_EN);
+	setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9), BCSR9_UCC3_RMII_EN);
+#endif
 }
 
-void disable_8569mds_brd_eeprom_write_protect()
+void disable_8569mds_brd_eeprom_write_protect(void)
 {
 	clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7), BCSR7_BRD_WRT_PROTECT);
 }