X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=board%2Ffreescale%2Fmpc8548cds%2Ftlb.c;h=994a32dd92ad04267c9dca1c3c8b813b2f13a989;hb=65cc0e2a65d2c9f107b2f42db6396d9ade6c5ad8;hp=b21f71bd12be82410a8fc31036b2c1aee48ed5cb;hpb=39166b5c9e7160761419f816f995b1d8029aa4a7;p=platform%2Fkernel%2Fu-boot.git

diff --git a/board/freescale/mpc8548cds/tlb.c b/board/freescale/mpc8548cds/tlb.c
index b21f71b..994a32d 100644
--- a/board/freescale/mpc8548cds/tlb.c
+++ b/board/freescale/mpc8548cds/tlb.c
@@ -1,26 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008, 2011 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2000
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
  */
 
 #include <common.h>
@@ -28,77 +11,76 @@
 
 struct fsl_e_tlb_entry tlb_table[] = {
 	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, CFG_SYS_INIT_RAM_ADDR,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024 , CFG_SYS_INIT_RAM_ADDR + 4 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024 , CFG_SYS_INIT_RAM_ADDR + 8 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024 , CFG_SYS_INIT_RAM_ADDR + 12 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
 
+	/* TLB 1 */
 	/*
-	 * TLB 0:	16M	Non-cacheable, guarded
-	 * 0xff000000	16M	FLASH
-	 * Out of reset this entry is only 4K.
+	 * Entry 0:
+	 * FLASH(cover boot page)	16M	Non-cacheable, guarded
 	 */
-	SET_TLB_ENTRY(1, CFG_BOOT_BLOCK, CFG_BOOT_BLOCK,
+	SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 0, BOOKE_PAGESZ_16M, 1),
 
 	/*
-	 * TLB 1:	1G	Non-cacheable, guarded
-	 * 0x80000000	1G	PCI1/PCIE  8,9,a,b
+	 * Entry 1:
+	 * CCSRBAR	1M	Non-cacheable, guarded
 	 */
-	SET_TLB_ENTRY(1, CFG_PCI_PHYS, CFG_PCI_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 1, BOOKE_PAGESZ_1G, 1),
+		      0, 1, BOOKE_PAGESZ_1M, 1),
 
-#ifdef CFG_RIO_MEM_PHYS
 	/*
-	 * TLB 2:	256M	Non-cacheable, guarded
+	 * Entry 2:
+	 * LBC SDRAM	64M	Cacheable, non-guarded
 	 */
-	SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 2, BOOKE_PAGESZ_256M, 1),
+	SET_TLB_ENTRY(1, CFG_SYS_LBC_SDRAM_BASE,
+		      CFG_SYS_LBC_SDRAM_BASE_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
+		      0, 2, BOOKE_PAGESZ_64M, 1),
 
 	/*
-	 * TLB 3:	256M	Non-cacheable, guarded
+	 * Entry 3:
+	 * CADMUS registers	1M	Non-cacheable, guarded
 	 */
-	SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000,
+	SET_TLB_ENTRY(1, CADMUS_BASE_ADDR, CADMUS_BASE_ADDR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 3, BOOKE_PAGESZ_256M, 1),
-#endif
+		      0, 3, BOOKE_PAGESZ_1M, 1),
+
 	/*
-	 * TLB 5:	64M	Non-cacheable, guarded
-	 * 0xe000_0000	1M	CCSRBAR
-	 * 0xe200_0000	1M	PCI1 IO
-	 * 0xe210_0000	1M	PCI2 IO
-	 * 0xe300_0000	1M	PCIe IO
+	 * Entry 4:
+	 * PCI and PCIe MEM	1G	Non-cacheable, guarded
 	 */
-	SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR,
+	SET_TLB_ENTRY(1, CFG_SYS_PCI1_MEM_VIRT, CFG_SYS_PCI1_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 5, BOOKE_PAGESZ_64M, 1),
+		      0, 4, BOOKE_PAGESZ_1G, 1),
 
 	/*
-	 * TLB 6:	64M	Cacheable, non-guarded
-	 * 0xf000_0000	64M	LBC SDRAM
+	 * Entry 5:
+	 * PCI1 IO	1M	Non-cacheable, guarded
 	 */
-	SET_TLB_ENTRY(1, CFG_LBC_CACHE_BASE, CFG_LBC_CACHE_BASE,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 6, BOOKE_PAGESZ_64M, 1),
+	SET_TLB_ENTRY(1, CFG_SYS_PCI1_IO_VIRT, CFG_SYS_PCI1_IO_PHYS,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 5, BOOKE_PAGESZ_1M, 1),
 
 	/*
-	 * TLB 7:	64M	Non-cacheable, guarded
-	 * 0xf8000000	64M	CADMUS registers, relocated L2SRAM
+	 * Entry 6:
+	 * PCIe IO	1M	Non-cacheable, guarded
 	 */
-	SET_TLB_ENTRY(1, CFG_LBC_NONCACHE_BASE, CFG_LBC_NONCACHE_BASE,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 7, BOOKE_PAGESZ_64M, 1),
+	SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 6, BOOKE_PAGESZ_1M, 1),
 };
 
 int num_tlb_entries = ARRAY_SIZE(tlb_table);