X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=board%2Ffreescale%2Fmpc8360erdk%2Fmpc8360erdk.c;h=fef230bfbd5683bead9042b7cd13ceec08f302c9;hb=1a4596601fd395f3afb8f82f3f840c5e00bdd57a;hp=98ec6abd27971d5f0524fbca75b1ee87731978e3;hpb=8d79953d03e6c5b24215609997dafe4daa623cd6;p=platform%2Fkernel%2Fu-boot.git diff --git a/board/freescale/mpc8360erdk/mpc8360erdk.c b/board/freescale/mpc8360erdk/mpc8360erdk.c index 98ec6ab..fef230b 100644 --- a/board/freescale/mpc8360erdk/mpc8360erdk.c +++ b/board/freescale/mpc8360erdk/mpc8360erdk.c @@ -8,17 +8,13 @@ * Copyright (C) 2007 MontaVista Software, Inc. * Anton Vorontsov * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. + * SPDX-License-Identifier: GPL-2.0+ */ #include #include #include #include -#include #include #include #include @@ -187,18 +183,30 @@ const qe_iop_conf_t qe_iop_conf_tab[] = { {1, 7, 1, 0, 0}, /* LVDS_BKLT_CTR */ {2, 16, 1, 0, 0}, /* LVDS_BKLT_EN */ + /* AD7843 ADC/Touchscreen controller */ + {4, 14, 1, 0, 0}, /* SPI_nCS0 */ + {4, 28, 3, 0, 3}, /* SPI_MOSI */ + {4, 29, 3, 0, 3}, /* SPI_MISO */ + {4, 30, 3, 0, 3}, /* SPI_CLK */ + + /* Freescale QUICC Engine USB Host Controller (FHCI) */ + {1, 2, 1, 0, 3}, /* USBOE */ + {1, 3, 1, 0, 3}, /* USBTP */ + {1, 8, 1, 0, 1}, /* USBTN */ + {1, 9, 2, 1, 3}, /* USBRP */ + {1, 10, 2, 0, 3}, /* USBRXD */ + {1, 11, 2, 1, 3}, /* USBRN */ + {2, 20, 2, 0, 1}, /* CLK21 */ + {4, 20, 1, 0, 0}, /* SPEED */ + {4, 21, 1, 0, 0}, /* SUSPND */ + /* END of table */ {0, 0, 0, 0, QE_IOP_TAB_END}, }; -int board_early_init_f(void) -{ - return 0; -} - int board_early_init_r(void) { - void *reg = (void *)(CFG_IMMR + 0x14a8); + void *reg = (void *)(CONFIG_SYS_IMMR + 0x14a8); u32 val; /* @@ -217,12 +225,12 @@ int board_early_init_r(void) int fixed_sdram(void) { - volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; u32 msize = 0; u32 ddr_size; u32 ddr_size_log2; - msize = CFG_DDR_SIZE; + msize = CONFIG_SYS_DDR_SIZE; for (ddr_size = msize << 20, ddr_size_log2 = 0; (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) { if (ddr_size & 1) @@ -232,40 +240,40 @@ int fixed_sdram(void) im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); - im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS; - im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG; - im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; - im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; - im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; - im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG; - im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2; - im->ddr.sdram_mode = CFG_DDR_MODE; - im->ddr.sdram_mode2 = CFG_DDR_MODE2; - im->ddr.sdram_interval = CFG_DDR_INTERVAL; - im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL; + im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS; + im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; + im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; + im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; + im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; + im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; + im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; + im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; + im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; + im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; + im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL; udelay(200); im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; return msize; } -long int initdram(int board_type) +phys_size_t initdram(int board_type) { -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) extern void ddr_enable_ecc(unsigned int dram_size); #endif - volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; u32 msize = 0; if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) return -1; /* DDR SDRAM - Main SODIMM */ - im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; msize = fixed_sdram(); -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) /* * Initialize DDR ECC byte */ @@ -284,33 +292,33 @@ int checkboard(void) static struct pci_region pci_regions[] = { { - .bus_start = CFG_PCI1_MEM_BASE, - .phys_start = CFG_PCI1_MEM_PHYS, - .size = CFG_PCI1_MEM_SIZE, + .bus_start = CONFIG_SYS_PCI1_MEM_BASE, + .phys_start = CONFIG_SYS_PCI1_MEM_PHYS, + .size = CONFIG_SYS_PCI1_MEM_SIZE, .flags = PCI_REGION_MEM | PCI_REGION_PREFETCH, }, { - .bus_start = CFG_PCI1_MMIO_BASE, - .phys_start = CFG_PCI1_MMIO_PHYS, - .size = CFG_PCI1_MMIO_SIZE, + .bus_start = CONFIG_SYS_PCI1_MMIO_BASE, + .phys_start = CONFIG_SYS_PCI1_MMIO_PHYS, + .size = CONFIG_SYS_PCI1_MMIO_SIZE, .flags = PCI_REGION_MEM, }, { - .bus_start = CFG_PCI1_IO_BASE, - .phys_start = CFG_PCI1_IO_PHYS, - .size = CFG_PCI1_IO_SIZE, + .bus_start = CONFIG_SYS_PCI1_IO_BASE, + .phys_start = CONFIG_SYS_PCI1_IO_PHYS, + .size = CONFIG_SYS_PCI1_IO_SIZE, .flags = PCI_REGION_IO, }, }; void pci_init_board(void) { - volatile immap_t *immr = (volatile immap_t *)CFG_IMMR; + volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; volatile law83xx_t *pci_law = immr->sysconf.pcilaw; struct pci_region *reg[] = { pci_regions, }; -#if defined(PCI_33M) +#if defined(CONFIG_PCI_33M) clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 | OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR; printf("PCI clock is 33MHz\n"); @@ -322,13 +330,13 @@ void pci_init_board(void) udelay(2000); /* Configure PCI Local Access Windows */ - pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR; + pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; - pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; + pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; - mpc83xx_pci_init(1, reg, 0); + mpc83xx_pci_init(1, reg); } #if defined(CONFIG_OF_BOARD_SETUP)