X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=board%2Ffreescale%2Fmpc8349itx%2Fmpc8349itx.c;h=803d722806046ab3fc296631b6094d0641e9895a;hb=c2120fbfbc4d1f6953228f86be8bdbf38bacfdab;hp=56475795b68246c4cf7448cf52c71ff27c1c9bfc;hpb=e9aecdec153ae166739858e6a570432449b979f7;p=kernel%2Fu-boot.git

diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c
index 5647579..803d722 100644
--- a/board/freescale/mpc8349itx/mpc8349itx.c
+++ b/board/freescale/mpc8349itx/mpc8349itx.c
@@ -1,23 +1,7 @@
 /*
  * Copyright (C) Freescale Semiconductor, Inc. 2006.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
@@ -43,23 +27,27 @@
 int fixed_sdram(void)
 {
 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	u32 ddr_size;		/* The size of RAM, in bytes */
-	u32 ddr_size_log2 = 0;
-
-	for (ddr_size = CONFIG_SYS_DDR_SIZE * 0x100000; ddr_size > 1; ddr_size >>= 1) {
-		if (ddr_size & 1) {
-			return -1;
-		}
-		ddr_size_log2++;
-	}
+	/* The size of RAM, in bytes */
+	u32 ddr_size = CONFIG_SYS_DDR_SIZE << 20;
+	u32 ddr_size_log2 = __ilog2(ddr_size);
 
 	im->sysconf.ddrlaw[0].ar =
 	    LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
 	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
 
-	/* Only one CS0 for DDR */
-	im->ddr.csbnds[0].csbnds = 0x0000000f;
-	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG;
+#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
+#warning Chip select bounds is only configurable in 16MB increments
+#endif
+	im->ddr.csbnds[0].csbnds =
+		((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+		(((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
+				CSBNDS_EA_SHIFT) & CSBNDS_EA);
+	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
+
+	/* Only one CS for DDR */
+	im->ddr.cs_config[1] = 0;
+	im->ddr.cs_config[2] = 0;
+	im->ddr.cs_config[3] = 0;
 
 	debug("cs0_bnds = 0x%08x\n", im->ddr.csbnds[0].csbnds);
 	debug("cs0_config = 0x%08x\n", im->ddr.cs_config[0]);
@@ -259,8 +247,7 @@ int misc_init_r(void)
 {
 	int rc = 0;
 
-#ifdef CONFIG_HARD_I2C
-
+#if defined(CONFIG_SYS_I2C)
 	unsigned int orig_bus = i2c_get_bus_num();
 	u8 i2c_data;