X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=board%2Ffreescale%2Fcorenet_ds%2Feth_superhydra.c;h=55bac0f7615d6771739158cfd2debcc57c577601;hb=cd9b71c3f629c97a0e516d2ad2d2e4baae74d440;hp=1962b7e3c73b897b4353ddac0d405d746cd285a6;hpb=83d290c56fab2d38cd1ab4c4cc7099559c1d5046;p=platform%2Fkernel%2Fu-boot.git

diff --git a/board/freescale/corenet_ds/eth_superhydra.c b/board/freescale/corenet_ds/eth_superhydra.c
index 1962b7e..55bac0f 100644
--- a/board/freescale/corenet_ds/eth_superhydra.c
+++ b/board/freescale/corenet_ds/eth_superhydra.c
@@ -48,6 +48,8 @@
  */
 
 #include <common.h>
+#include <log.h>
+#include <net.h>
 #include <netdev.h>
 #include <asm/fsl_serdes.h>
 #include <fm_eth.h>
@@ -315,6 +317,9 @@ void fdt_fixup_board_enet(void *fdt)
 			}
 			break;
 		case PHY_INTERFACE_MODE_RGMII:
+		case PHY_INTERFACE_MODE_RGMII_TXID:
+		case PHY_INTERFACE_MODE_RGMII_RXID:
+		case PHY_INTERFACE_MODE_RGMII_ID:
 			fdt_status_okay_by_alias(fdt, "hydra_rg");
 			debug("Enabled MDIO node hydra_rg\n");
 			break;
@@ -351,6 +356,9 @@ void fdt_fixup_board_enet(void *fdt)
 			}
 			break;
 		case PHY_INTERFACE_MODE_RGMII:
+		case PHY_INTERFACE_MODE_RGMII_TXID:
+		case PHY_INTERFACE_MODE_RGMII_RXID:
+		case PHY_INTERFACE_MODE_RGMII_ID:
 			fdt_status_okay_by_alias(fdt, "hydra_rg");
 			debug("Enabled MDIO node hydra_rg\n");
 			break;
@@ -413,7 +421,7 @@ void fdt_fixup_board_enet(void *fdt)
  * 0x36                |                 |                 |
  */
 
-int board_eth_init(bd_t *bis)
+int board_eth_init(struct bd_info *bis)
 {
 #ifdef CONFIG_FMAN_ENET
 	struct fsl_pq_mdio_info dtsec_mdio_info;
@@ -555,6 +563,9 @@ int board_eth_init(bd_t *bis)
 			miiphy_get_dev_by_name("SUPER_HYDRA_FM1_SGMII_MDIO"));
 			break;
 		case PHY_INTERFACE_MODE_RGMII:
+		case PHY_INTERFACE_MODE_RGMII_TXID:
+		case PHY_INTERFACE_MODE_RGMII_RXID:
+		case PHY_INTERFACE_MODE_RGMII_ID:
 			/*
 			 * FM1 DTSEC5 is routed via EC1 to the first on-board
 			 * RGMII port. FM2 DTSEC5 is routed via EC2 to the
@@ -572,7 +583,7 @@ int board_eth_init(bd_t *bis)
 			fm_info_set_mdio(i,
 				miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO"));
 			break;
-		case PHY_INTERFACE_MODE_NONE:
+		case PHY_INTERFACE_MODE_NA:
 			fm_info_set_phy_address(i, 0);
 			break;
 		default:
@@ -702,6 +713,9 @@ int board_eth_init(bd_t *bis)
 
 			break;
 		case PHY_INTERFACE_MODE_RGMII:
+		case PHY_INTERFACE_MODE_RGMII_TXID:
+		case PHY_INTERFACE_MODE_RGMII_RXID:
+		case PHY_INTERFACE_MODE_RGMII_ID:
 			/*
 			 * FM1 DTSEC5 is routed via EC1 to the first on-board
 			 * RGMII port. FM2 DTSEC5 is routed via EC2 to the
@@ -719,7 +733,7 @@ int board_eth_init(bd_t *bis)
 			fm_info_set_mdio(i,
 			miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO"));
 			break;
-		case PHY_INTERFACE_MODE_NONE:
+		case PHY_INTERFACE_MODE_NA:
 			fm_info_set_phy_address(i, 0);
 			break;
 		default: