X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=board%2Ffreescale%2Fcorenet_ds%2Fddr.c;h=38f13ce4b2ec39ee30e71015bc044662f6b7e8aa;hb=83d290c56fab2d38cd1ab4c4cc7099559c1d5046;hp=b93701571b7fd19ac7c8fc46149d1e6f9559f07d;hpb=dd620b26332eb1e9fc0216760909c4046ba09745;p=platform%2Fkernel%2Fu-boot.git diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c index b937015..38f13ce 100644 --- a/board/freescale/corenet_ds/ddr.c +++ b/board/freescale/corenet_ds/ddr.c @@ -1,17 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Copyright 2009-2011 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. */ #include #include #include #include -#include -#include +#include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -21,7 +18,7 @@ DECLARE_GLOBAL_DATA_PTR; * Fixed sdram init -- doesn't use serial presence detect. */ extern fixed_ddr_parm_t fixed_ddr_parm_0[]; -#if (CONFIG_NUM_DDR_CONTROLLERS == 2) +#if (CONFIG_SYS_NUM_DDR_CTLRS == 2) extern fixed_ddr_parm_t fixed_ddr_parm_1[]; #endif @@ -56,14 +53,14 @@ phys_size_t fixed_sdram(void) ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN; - fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0); + fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0); -#if (CONFIG_NUM_DDR_CONTROLLERS == 2) +#if (CONFIG_SYS_NUM_DDR_CTLRS == 2) memcpy(&ddr_cfg_regs, fixed_ddr_parm_1[i].ddr_settings, sizeof(ddr_cfg_regs)); ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN; - fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 1); + fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 1, 0); #endif /* @@ -78,7 +75,7 @@ phys_size_t fixed_sdram(void) return 0; } } else { -#if (CONFIG_NUM_DDR_CONTROLLERS == 2) +#if (CONFIG_SYS_NUM_DDR_CTLRS == 2) /* We require both controllers have identical DIMMs */ lawbar1_target_id = LAW_TRGT_IF_DDR_1; if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, @@ -107,101 +104,138 @@ phys_size_t fixed_sdram(void) return ddr_size; } -typedef struct { - u32 datarate_mhz_low; - u32 datarate_mhz_high; +struct board_specific_parameters { u32 n_ranks; + u32 datarate_mhz_high; u32 clk_adjust; u32 wrlvl_start; u32 cpo; u32 write_data_delay; - u32 force_2T; -} board_specific_parameters_t; + u32 force_2t; +}; -/* ranges for parameters: - * wr_data_delay = 0-6 - * clk adjust = 0-8 - * cpo 2-0x1E (30) +/* + * This table contains all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. */ - - -/* XXX: these values need to be checked for all interleaving modes. */ -/* XXX: No reliable dual-rank 800 MHz setting has been found. It may - * seem reliable, but errors will appear when memory intensive - * program is run. */ -/* XXX: Single rank at 800 MHz is OK. */ -const board_specific_parameters_t board_specific_parameters[][30] = { - { +static const struct board_specific_parameters udimm0[] = { /* * memory controller 0 - * lo| hi| num| clk| wrlvl | cpo |wrdata|2T - * mhz| mhz|ranks|adjst| start | delay| + * num| hi| clk| wrlvl | cpo |wrdata|2T + * ranks| mhz|adjst| start | |delay | */ - { 0, 850, 4, 4, 6, 0xff, 2, 0}, - {851, 950, 4, 5, 7, 0xff, 2, 0}, - {951, 1050, 4, 5, 8, 0xff, 2, 0}, - {1051, 1250, 4, 5, 10, 0xff, 2, 0}, - {1251, 1350, 4, 5, 11, 0xff, 2, 0}, - { 0, 850, 2, 5, 6, 0xff, 2, 0}, - {851, 950, 2, 5, 7, 0xff, 2, 0}, - {951, 1050, 2, 5, 7, 0xff, 2, 0}, - {1051, 1250, 2, 4, 6, 0xff, 2, 0}, - {1251, 1350, 2, 5, 7, 0xff, 2, 0}, - }, - - { + {4, 850, 4, 6, 0xff, 2, 0}, + {4, 950, 5, 7, 0xff, 2, 0}, + {4, 1050, 5, 8, 0xff, 2, 0}, + {4, 1250, 5, 10, 0xff, 2, 0}, + {4, 1350, 5, 11, 0xff, 2, 0}, + {4, 1666, 5, 12, 0xff, 2, 0}, + {2, 850, 5, 6, 0xff, 2, 0}, + {2, 1050, 5, 7, 0xff, 2, 0}, + {2, 1250, 4, 6, 0xff, 2, 0}, + {2, 1350, 5, 7, 0xff, 2, 0}, + {2, 1666, 5, 8, 0xff, 2, 0}, + {1, 1250, 4, 6, 0xff, 2, 0}, + {1, 1335, 4, 7, 0xff, 2, 0}, + {1, 1666, 4, 8, 0xff, 2, 0}, + {} +}; + +/* + * The two slots have slightly different timing. The center values are good + * for both slots. We use identical speed tables for them. In future use, if + * DIMMs have fewer center values that require two separated tables, copy the + * udimm0 table to udimm1 and make changes to clk_adjust and wrlvl_start. + */ +static const struct board_specific_parameters *udimms[] = { + udimm0, + udimm0, +}; + +static const struct board_specific_parameters rdimm0[] = { /* - * memory controller 1 - * lo| hi| num| clk| wrlvl | cpo |wrdata|2T - * mhz| mhz|ranks|adjst| start | delay| + * memory controller 0 + * num| hi| clk| wrlvl | cpo |wrdata|2T + * ranks| mhz|adjst| start | |delay | */ - { 0, 850, 4, 4, 6, 0xff, 2, 0}, - {851, 950, 4, 5, 7, 0xff, 2, 0}, - {951, 1050, 4, 5, 8, 0xff, 2, 0}, - {1051, 1250, 4, 5, 10, 0xff, 2, 0}, - {1251, 1350, 4, 5, 11, 0xff, 2, 0}, - { 0, 850, 2, 5, 6, 0xff, 2, 0}, - {851, 950, 2, 5, 7, 0xff, 2, 0}, - {951, 1050, 2, 5, 7, 0xff, 2, 0}, - {1051, 1250, 2, 4, 6, 0xff, 2, 0}, - {1251, 1350, 2, 5, 7, 0xff, 2, 0}, - } + {4, 850, 4, 6, 0xff, 2, 0}, + {4, 950, 5, 7, 0xff, 2, 0}, + {4, 1050, 5, 8, 0xff, 2, 0}, + {4, 1250, 5, 10, 0xff, 2, 0}, + {4, 1350, 5, 11, 0xff, 2, 0}, + {4, 1666, 5, 12, 0xff, 2, 0}, + {2, 850, 4, 6, 0xff, 2, 0}, + {2, 1050, 4, 7, 0xff, 2, 0}, + {2, 1666, 4, 8, 0xff, 2, 0}, + {1, 850, 4, 5, 0xff, 2, 0}, + {1, 950, 4, 7, 0xff, 2, 0}, + {1, 1666, 4, 8, 0xff, 2, 0}, + {} +}; + +/* + * The two slots have slightly different timing. See comments above. + */ +static const struct board_specific_parameters *rdimms[] = { + rdimm0, + rdimm0, }; void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) { - const board_specific_parameters_t *pbsp = - &(board_specific_parameters[ctrl_num][0]); - u32 num_params = sizeof(board_specific_parameters[ctrl_num]) / - sizeof(board_specific_parameters[0][0]); - u32 i; + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; ulong ddr_freq; + if (ctrl_num > 1) { + printf("Wrong parameter for controller number %d", ctrl_num); + return; + } + if (!pdimm->n_ranks) + return; + + if (popts->registered_dimm_en) + pbsp = rdimms[ctrl_num]; + else + pbsp = udimms[ctrl_num]; + + /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr * freqency and n_banks specified in board_specific_parameters table. */ ddr_freq = get_ddr_freq(0) / 1000000; - for (i = 0; i < num_params; i++) { - if (ddr_freq >= pbsp->datarate_mhz_low && - ddr_freq <= pbsp->datarate_mhz_high && - pdimm[0].n_ranks == pbsp->n_ranks) { - popts->cpo_override = pbsp->cpo; - popts->write_data_delay = pbsp->write_data_delay; - popts->clk_adjust = pbsp->clk_adjust; - popts->wrlvl_start = pbsp->wrlvl_start; - popts->twoT_en = pbsp->force_2T; - break; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->cpo_override = pbsp->cpo; + popts->write_data_delay = + pbsp->write_data_delay; + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->twot_en = pbsp->force_2t; + goto found; + } + pbsp_highest = pbsp; } pbsp++; } - if (i == num_params) { - printf("Warning: board specific timing not found " - "for data rate %lu MT/s!\n", ddr_freq); + if (pbsp_highest) { + printf("Error: board specific timing not found " + "for data rate %lu MT/s!\n" + "Trying to use the highest speed (%u) parameters\n", + ddr_freq, pbsp_highest->datarate_mhz_high); + popts->cpo_override = pbsp_highest->cpo; + popts->write_data_delay = pbsp_highest->write_data_delay; + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->wrlvl_start = pbsp_highest->wrlvl_start; + popts->twot_en = pbsp_highest->force_2t; + } else { + panic("DIMM is not supported by this board"); } - +found: /* * Factors to consider for half-strength driver enable: * - number of DIMMs installed @@ -223,23 +257,9 @@ void fsl_ddr_board_options(memctl_options_t *popts, /* DHC_EN =1, ODT = 60 Ohm */ popts->ddr_cdr1 = DDR_CDR1_DHC_EN; - - /* override SPD values. rcw_2 should vary at differnt speed */ - if (pdimm[0].registered_dimm == 1) { - popts->rcw_override = 1; - popts->rcw_1 = 0x000a5a00; - if (ddr_freq <= 800) - popts->rcw_2 = 0x00000000; - else if (ddr_freq <= 1066) - popts->rcw_2 = 0x00100000; - else if (ddr_freq <= 1333) - popts->rcw_2 = 0x00200000; - else - popts->rcw_2 = 0x00300000; - } } -phys_size_t initdram(int board_type) +int dram_init(void) { phys_size_t dram_size; @@ -257,5 +277,7 @@ phys_size_t initdram(int board_type) dram_size *= 0x100000; debug(" DDR: "); - return dram_size; + gd->ram_size = dram_size; + + return 0; }