X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=board%2Fesd%2Fcpci2dp%2Fcpci2dp.c;h=00c7024a85287231c707b7693cfa7a3a028557dc;hb=297a65873d2cb2bd296253af51f59cc1391afbff;hp=0949a7d634fa1615270f97ed03f94046506a349b;hpb=7644f16f6bf4335899603a1065bdf2c7c62bb915;p=platform%2Fkernel%2Fu-boot.git diff --git a/board/esd/cpci2dp/cpci2dp.c b/board/esd/cpci2dp/cpci2dp.c index 0949a7d..00c7024 100644 --- a/board/esd/cpci2dp/cpci2dp.c +++ b/board/esd/cpci2dp/cpci2dp.c @@ -12,7 +12,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -23,22 +23,28 @@ #include #include +#include #include #include +DECLARE_GLOBAL_DATA_PTR; + int board_early_init_f (void) { - unsigned long cntrl0Reg; + unsigned long CPC0_CR0Reg; /* - * Setup GPIO pins (CS4 as GPIO) + * Setup GPIO pins */ - cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | 0x00800000); + CPC0_CR0Reg = mfdcr(CPC0_CR0); + mtdcr(CPC0_CR0, CPC0_CR0Reg | + ((CONFIG_SYS_EEPROM_WP | CONFIG_SYS_PB_LED | + CONFIG_SYS_SELF_RST | CONFIG_SYS_INTA_FAKE) << 5)); - out32(GPIO0_OR, CFG_INTA_FAKE | CFG_EEPROM_WP); /* set output pins to high */ - out32(GPIO0_ODR, CFG_INTA_FAKE); /* INTA# is open drain */ - out32(GPIO0_TCR, CFG_INTA_FAKE | CFG_EEPROM_WP); /* setup for output */ + /* set output pins to high */ + out_be32((void *)GPIO0_OR, CONFIG_SYS_EEPROM_WP); + /* setup for output (LED=off) */ + out_be32((void *)GPIO0_TCR, CONFIG_SYS_EEPROM_WP | CONFIG_SYS_PB_LED); /* * IRQ 0-15 405GP internally generated; active high; level sensitive @@ -52,29 +58,21 @@ int board_early_init_f (void) * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive * IRQ 31 (EXT IRQ 6) unused */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ - mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(uicer, 0x00000000); /* disable all ints */ + mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ + mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(uictr, 0x10000000); /* set int trigger levels */ + mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ return 0; } - -int misc_init_f (void) -{ - return 0; /* dummy implementation */ -} - - int misc_init_r (void) { - DECLARE_GLOBAL_DATA_PTR; - unsigned long cntrl0Reg; + unsigned long CPC0_CR0Reg; /* adjust flash start and offset */ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; @@ -83,8 +81,8 @@ int misc_init_r (void) /* * Select cts (and not dsr) on uart1 */ - cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | 0x00001000); + CPC0_CR0Reg = mfdcr(CPC0_CR0); + mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000); return (0); } @@ -95,7 +93,7 @@ int misc_init_r (void) */ int checkboard (void) { - unsigned char str[64]; + char str[64]; int i = getenv_r ("serial#", str, sizeof(str)); puts ("Board: "); @@ -113,58 +111,36 @@ int checkboard (void) return 0; } -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ - unsigned long val; - - mtdcr(memcfga, mem_mb0cf); - val = mfdcr(memcfgd); - - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); -} - -/* ------------------------------------------------------------------------- */ - -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 64 MB - ok\n"); - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -#if defined(CFG_EEPROM_WREN) +#if defined(CONFIG_SYS_EEPROM_WREN) /* Input: I2C address of EEPROM device to enable. - * -1: deliver current state - * 0: disable write + * -1: deliver current state + * 0: disable write * 1: enable write - * Returns: -1: wrong device address - * 0: dis-/en- able done + * Returns: -1: wrong device address + * 0: dis-/en- able done * 0/1: current state if was -1. */ int eeprom_write_enable (unsigned dev_addr, int state) { - if (CFG_I2C_EEPROM_ADDR != dev_addr) { + if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) { return -1; - } - else { + } else { switch (state) { case 1: /* Enable write access, clear bit GPIO_SINT2. */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_EEPROM_WP); + out_be32((void *)GPIO0_OR, + in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP); state = 0; break; case 0: /* Disable write access, set bit GPIO_SINT2. */ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP); + out_be32((void *)GPIO0_OR, + in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP); state = 0; break; default: /* Read current status back. */ - state = (0 == (in32(GPIO0_OR) & CFG_EEPROM_WP)); + state = (0 == (in_be32((void *)GPIO0_OR) & + CONFIG_SYS_EEPROM_WP)); break; } } @@ -172,7 +148,7 @@ int eeprom_write_enable (unsigned dev_addr, int state) { } #endif -#if defined(CFG_EEPROM_WREN) +#if defined(CONFIG_SYS_EEPROM_WREN) int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { int query = argc == 1; @@ -180,24 +156,21 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (query) { /* Query write access state. */ - state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1); + state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1); if (state < 0) { puts ("Query of write access state failed.\n"); - } - else { + } else { printf ("Write access for device 0x%0x is %sabled.\n", - CFG_I2C_EEPROM_ADDR, state ? "en" : "dis"); + CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis"); state = 0; } - } - else { + } else { if ('0' == argv[1][0]) { /* Disable write access. */ - state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0); - } - else { + state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0); + } else { /* Enable write access. */ - state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1); + state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1); } if (state < 0) { puts ("Setup of write access state failed.\n"); @@ -208,8 +181,8 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD( - eepwren, 2, 0, do_eep_wren, - "eepwren - Enable / disable / query EEPROM write access\n", - NULL - ); -#endif /* #if defined(CFG_EEPROM_WREN) */ + eepwren, 2, 0, do_eep_wren, + "Enable / disable / query EEPROM write access", + "" +); +#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */