X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=board%2Fesd%2Fcms700%2Fcms700.c;h=7a92401893d9f101171df0b05b5dfdde4b075c3a;hb=297a65873d2cb2bd296253af51f59cc1391afbff;hp=e283a92764bd743904676814477b23ff1e457fd6;hpb=4e3ccd26925e5ada78dd89779838f052dffe3e67;p=platform%2Fkernel%2Fu-boot.git diff --git a/board/esd/cms700/cms700.c b/board/esd/cms700/cms700.c index e283a92..7a92401 100644 --- a/board/esd/cms700/cms700.c +++ b/board/esd/cms700/cms700.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2005 + * (C) Copyright 2005-2007 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com * * See file CREDITS for list of people who contributed to this @@ -23,21 +23,14 @@ #include #include +#include #include #include +DECLARE_GLOBAL_DATA_PTR; extern void lxt971_no_sleep(void); - -/* fpga configuration data - not compressed, generated by bin2c */ -const unsigned char fpgadata[] = -{ -#include "fpgadata.c" -}; -int filesize = sizeof(fpgadata); - - int board_early_init_f (void) { /* @@ -63,46 +56,29 @@ int board_early_init_f (void) /* * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us */ - mtebc (epcr, 0xa8400000); /* ebc always driven */ + mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */ /* * Reset CPLD via GPIO12 (CS3) pin */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_PLD_RESET); + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_PLD_RESET); udelay(1000); /* wait 1ms */ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_PLD_RESET); + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_PLD_RESET); udelay(1000); /* wait 1ms */ return 0; } - -/* ------------------------------------------------------------------------- */ - -int misc_init_f (void) -{ - return 0; /* dummy implementation */ -} - - int misc_init_r (void) { - DECLARE_GLOBAL_DATA_PTR; - /* adjust flash start and offset */ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; gd->bd->bi_flashoffset = 0; - /* - * Setup and enable EEPROM write protection - */ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP); - /* - * Set NAND-FLASH GPIO signals to default + * Setup and enable EEPROM write protection */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE); + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP); return (0); } @@ -111,14 +87,12 @@ int misc_init_r (void) /* * Check Board Identity: */ - +#define LED_REG (CONFIG_SYS_PLD_BASE + 0x1000) int checkboard (void) { char str[64]; int flashcnt; int delay; - volatile unsigned char *led_reg = (unsigned char *)((ulong)CFG_PLD_BASE + 0x1000); - volatile unsigned char *ver_reg = (unsigned char *)((ulong)CFG_PLD_BASE + 0x1001); puts ("Board: "); @@ -128,44 +102,28 @@ int checkboard (void) puts(str); } - printf(" (PLD-Version=%02d)\n", *ver_reg); + printf(" (PLD-Version=%02d)\n", + in_8((void *)(CONFIG_SYS_PLD_BASE + 0x1001))); /* * Flash LEDs */ for (flashcnt = 0; flashcnt < 3; flashcnt++) { - *led_reg = 0x00; /* LEDs off */ + out_8((void *)LED_REG, 0x00); /* LEDs off */ for (delay = 0; delay < 100; delay++) udelay(1000); - *led_reg = 0x0f; /* LEDs on */ + out_8((void *)LED_REG, 0x0f); /* LEDs on */ for (delay = 0; delay < 50; delay++) udelay(1000); } - *led_reg = 0x70; + out_8((void *)LED_REG, 0x70); return 0; } /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) -{ - unsigned long val; - - mtdcr(memcfga, mem_mb0cf); - val = mfdcr(memcfgd); - -#if 0 - printf("\nmb0cf=%x\n", val); /* test-only */ - printf("strap=%x\n", mfdcr(strap)); /* test-only */ -#endif - - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); -} - -/* ------------------------------------------------------------------------- */ - -#if defined(CFG_EEPROM_WREN) +#if defined(CONFIG_SYS_EEPROM_WREN) /* Input: I2C address of EEPROM device to enable. * -1: deliver current state * 0: disable write @@ -176,23 +134,23 @@ long int initdram (int board_type) */ int eeprom_write_enable (unsigned dev_addr, int state) { - if (CFG_I2C_EEPROM_ADDR != dev_addr) { + if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) { return -1; } else { switch (state) { case 1: /* Enable write access, clear bit GPIO_SINT2. */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_EEPROM_WP); + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP); state = 0; break; case 0: /* Disable write access, set bit GPIO_SINT2. */ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP); + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP); state = 0; break; default: /* Read current status back. */ - state = (0 == (in32(GPIO0_OR) & CFG_EEPROM_WP)); + state = (0 == (in_be32((void *)GPIO0_OR) & CONFIG_SYS_EEPROM_WP)); break; } } @@ -206,21 +164,21 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (query) { /* Query write access state. */ - state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1); + state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1); if (state < 0) { puts ("Query of write access state failed.\n"); } else { printf ("Write access for device 0x%0x is %sabled.\n", - CFG_I2C_EEPROM_ADDR, state ? "en" : "dis"); + CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis"); state = 0; } } else { if ('0' == argv[1][0]) { /* Disable write access. */ - state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0); + state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0); } else { /* Enable write access. */ - state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1); + state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1); } if (state < 0) { puts ("Setup of write access state failed.\n"); @@ -231,25 +189,13 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, - "eepwren - Enable / disable / query EEPROM write access\n", - NULL); -#endif /* #if defined(CFG_EEPROM_WREN) */ + "Enable / disable / query EEPROM write access", + "" +); +#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */ /* ------------------------------------------------------------------------- */ -#if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include -extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; - -void nand_init(void) -{ - nand_probe(CFG_NAND_BASE); - if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { - print_size(nand_dev_desc[0].totlen, "\n"); - } -} -#endif - void reset_phy(void) { #ifdef CONFIG_LXT971_NO_SLEEP