X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=board%2Fcray%2FL1%2FL1.c;h=8a06ecc66504e91f4aa4b8b3577c826e62a9b3b2;hb=3405f38a15eec5092ac47efe0829f10a24491c6e;hp=5264bafd4bd9b2e2542868c3e9ccef97b631ff0e;hpb=01026a6e613e1cfe580122fb5350677025f896fa;p=platform%2Fkernel%2Fu-boot.git

diff --git a/board/cray/L1/L1.c b/board/cray/L1/L1.c
index 5264baf..8a06ecc 100644
--- a/board/cray/L1/L1.c
+++ b/board/cray/L1/L1.c
@@ -139,8 +139,15 @@ int misc_init_r (void)
 	struct rtc_time tm;
 	char bootcmd[32];
 
-	hdr = (image_header_t *) (CFG_MONITOR_BASE - sizeof (image_header_t));
-	timestamp = (time_t) hdr->ih_time;
+	hdr = (image_header_t *) (CONFIG_SYS_MONITOR_BASE - image_get_header_size ());
+#if defined(CONFIG_FIT)
+	if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) {
+		puts ("Non legacy image format not supported\n");
+		return -1;
+	}
+#endif
+
+	timestamp = (time_t)image_get_time (hdr);
 	to_tm (timestamp, &tm);
 	printf ("Welcome to U-Boot on Cray L1. Compiled %4d-%02d-%02d  %2d:%02d:%02d (UTC)\n", tm.tm_year, tm.tm_mon, tm.tm_mday, tm.tm_hour, tm.tm_min, tm.tm_sec);
 
@@ -157,13 +164,13 @@ int misc_init_r (void)
 			setenv ("ethaddr", e);
 		}
 	}
-	sprintf (bootcmd,"autoscript %X",(unsigned)bootscript);
+	sprintf (bootcmd,"source %X",(unsigned)bootscript);
 	setenv ("bootcmd", bootcmd);
 	return (0);
 }
 
 /* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
 {
 	return (L1_MEMSIZE);
 }
@@ -174,9 +181,9 @@ int rtc_get (struct rtc_time *tmp)
 {
 	return 0;
 }
-void rtc_set (struct rtc_time *tmp)
+int rtc_set (struct rtc_time *tmp)
 {
-	return;
+	return 0;
 }
 void rtc_reset (void)
 {
@@ -198,13 +205,13 @@ static void init_sdram (void)
 /* To set the appropriate timings, we need to know the SDRAM speed.	*/
 /* We can use the PLB speed since the SDRAM speed is the same as	*/
 /* the PLB speed. The PLB speed is the FBK divider times the		*/
-/* 405GP reference clock, which on the L1 is 25Mhz.			*/
-/* Thus, if FBK div is 2, SDRAM is 50Mhz; if FBK div is 3, SDRAM is	*/
-/* 150Mhz; if FBK is 3, SDRAM is 150Mhz.				*/
+/* 405GP reference clock, which on the L1 is 25MHz.			*/
+/* Thus, if FBK div is 2, SDRAM is 50MHz; if FBK div is 3, SDRAM is	*/
+/* 150MHz; if FBK is 3, SDRAM is 150MHz.				*/
 
 	/* divisor = ((mfdcr(strap)>> 28) & 0x3); */
 
-/* write SDRAM timing for 100Mhz. */
+/* write SDRAM timing for 100MHz. */
 	mtdcr (memcfga, mem_sdtr1);
 	mtdcr (memcfgd, 0x0086400D);