X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=board%2Fcpu87%2Fcpu87.c;h=01f90d2ebbe98c376301fed0e8da551692009dbd;hb=e2b1962977f9f05745344d55a81f709794d791d3;hp=e8c2614eb477dc953647cc4cc99bfa38ee174246;hpb=6587f7e1e98bfcb7910a47bae2eb51e9a5fbd4da;p=platform%2Fkernel%2Fu-boot.git

diff --git a/board/cpu87/cpu87.c b/board/cpu87/cpu87.c
index e8c2614..01f90d2 100644
--- a/board/cpu87/cpu87.c
+++ b/board/cpu87/cpu87.c
@@ -2,23 +2,7 @@
  * (C) Copyright 2001-2005
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
@@ -26,6 +10,7 @@
 #include <mpc8260.h>
 #include "cpu87.h"
 #include <pci.h>
+#include <netdev.h>
 
 /*
  * I/O Port configuration table
@@ -162,7 +147,7 @@ const iop_conf_t iop_conf_tab[4][32] = {
 	/* PD18 */ {   0,   0,   0,   0,   0,   0   }, /* PD18 */
 	/* PD17 */ {   0,   0,   0,   0,   0,   0   }, /* PD17 */
 	/* PD16 */ {   0,   0,   0,   0,   0,   0   }, /* PD16 */
-#if defined(CONFIG_SOFT_I2C)
+#if defined(CONFIG_SYS_I2C_SOFT)
 	/* PD15 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SDA */
 	/* PD14 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SCL */
 #else
@@ -226,7 +211,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
 	 */
 	maxsize = (1 + (~orx | 0x7fff)) / 2;
 
-	/* Since CFG_SDRAM_BASE is always 0 (??), we assume that
+	/* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that
 	 * we are configuring CS1 if base != 0
 	 */
 	sdmr_ptr = &memctl->memc_psdmr;
@@ -251,7 +236,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
 	 *  accessing the SDRAM with a single-byte transaction."
 	 *
 	 * The appropriate BRx/ORx registers have already been set when we
-	 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+	 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
 	 */
 
 	*sdmr_ptr = sdmr | PSDMR_OP_PREA;
@@ -262,7 +247,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
 		*base = c;
 
 	*sdmr_ptr = sdmr | PSDMR_OP_MRW;
-	*(base + CFG_MRS_OFFS) = c;	/* setting MR on address lines */
+	*(base + CONFIG_SYS_MRS_OFFS) = c;	/* setting MR on address lines */
 
 	*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
 	*base = c;
@@ -274,58 +259,57 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
 	return (size);
 }
 
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8260_t *memctl = &immap->im_memctl;
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	ulong size8, size9, size10;
 #endif
 	long psize;
 
 	psize = 32 * 1024 * 1024;
 
-	memctl->memc_mptpr = CFG_MPTPR;
-	memctl->memc_psrt = CFG_PSRT;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
+	memctl->memc_psrt = CONFIG_SYS_PSRT;
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	/* 60x SDRAM setup:
 	 */
-	size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
-			  (uchar *) CFG_SDRAM_BASE);
-	
-	size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL,
-			  (uchar *) CFG_SDRAM_BASE);
-	
-	size10 = try_init (memctl, CFG_PSDMR_10COL, CFG_OR2_10COL,
-			  (uchar *) CFG_SDRAM_BASE);
-	
+	size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
+			  (uchar *) CONFIG_SYS_SDRAM_BASE);
+
+	size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR2_9COL,
+			  (uchar *) CONFIG_SYS_SDRAM_BASE);
+
+	size10 = try_init (memctl, CONFIG_SYS_PSDMR_10COL, CONFIG_SYS_OR2_10COL,
+			  (uchar *) CONFIG_SYS_SDRAM_BASE);
+
 	psize = max(size8,max(size9,size10));
-	
+
 	if (psize == size8) {
-		psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
-				  (uchar *) CFG_SDRAM_BASE);
+		psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
+				  (uchar *) CONFIG_SYS_SDRAM_BASE);
 		printf ("(60x:8COL) ");
 	} else if (psize == size9){
-		psize = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL,
-				  (uchar *) CFG_SDRAM_BASE);
+		psize = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR2_9COL,
+				  (uchar *) CONFIG_SYS_SDRAM_BASE);
 		printf ("(60x:9COL) ");
 	} else
 		printf ("(60x:10COL) ");
 
-#endif	/* CFG_RAMBOOT */
+#endif	/* CONFIG_SYS_RAMBOOT */
 
 	icache_enable ();
 
 	return (psize);
 }
 
-#if (CONFIG_COMMANDS & CFG_CMD_DOC)
-extern void doc_probe (ulong physadr);
+#if defined(CONFIG_CMD_DOC)
 void doc_init (void)
 {
-	doc_probe (CFG_DOC_BASE);
+	doc_probe (CONFIG_SYS_DOC_BASE);
 }
 #endif
 
@@ -339,3 +323,8 @@ void pci_init_board(void)
 	pci_mpc8250_init(&hose);
 }
 #endif
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}