X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=board%2Fatc%2Fatc.c;h=c2b5a1f65cc17a54de8454c69739da7dc391eaff;hb=ea818dbbcd59300b56014ac2d67798a54994eb9b;hp=d2c6b3bfcd9bb257ca904abbabc8779e38bd21dc;hpb=c83bf6a2d00ef846c1fb2b0c60540f03ef203125;p=platform%2Fkernel%2Fu-boot.git

diff --git a/board/atc/atc.c b/board/atc/atc.c
index d2c6b3b..c2b5a1f 100644
--- a/board/atc/atc.c
+++ b/board/atc/atc.c
@@ -170,7 +170,7 @@ const iop_conf_t iop_conf_tab[4][32] = {
 	/* PD18 */ {   0,   0,   0,   0,   0,   0   }, /* PD18 */
 	/* PD17 */ {   0,   0,   0,   0,   0,   0   }, /* PD17 */
 	/* PD16 */ {   0,   0,   0,   0,   0,   0   }, /* PD16 */
-#if defined(CONFIG_SOFT_I2C)
+#if defined(CONFIG_SYS_I2C_SOFT)
 	/* PD15 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SDA */
 	/* PD14 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SCL */
 #else
@@ -281,7 +281,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
 	 */
 	maxsize = (1 + (~orx | 0x7fff)) / 2;
 
-	/* Since CFG_SDRAM_BASE is always 0 (??), we assume that
+	/* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that
 	 * we are configuring CS1 if base != 0
 	 */
 	sdmr_ptr = &memctl->memc_psdmr;
@@ -306,7 +306,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
 	 *  accessing the SDRAM with a single-byte transaction."
 	 *
 	 * The appropriate BRx/ORx registers have already been set when we
-	 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+	 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
 	 */
 
 	*sdmr_ptr = sdmr | PSDMR_OP_PREA;
@@ -317,7 +317,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
 		*base = c;
 
 	*sdmr_ptr = sdmr | PSDMR_OP_MRW;
-	*(base + CFG_MRS_OFFS) = c;	/* setting MR on address lines */
+	*(base + CONFIG_SYS_MRS_OFFS) = c;	/* setting MR on address lines */
 
 	*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
 	*base = c;
@@ -331,7 +331,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
 
 int misc_init_r(void)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8260_t *memctl = &immap->im_memctl;
 
 	upmconfig(UPMA, (uint *)rtc_table, sizeof(rtc_table) / sizeof(uint));
@@ -340,50 +340,49 @@ int misc_init_r(void)
 	return (0);
 }
 
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8260_t *memctl = &immap->im_memctl;
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	ulong size8, size9;
 #endif
 	long psize;
 
 	psize = 8 * 1024 * 1024;
 
-	memctl->memc_mptpr = CFG_MPTPR;
-	memctl->memc_psrt = CFG_PSRT;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
+	memctl->memc_psrt = CONFIG_SYS_PSRT;
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	/* 60x SDRAM setup:
 	 */
-	size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
-			  (uchar *) CFG_SDRAM_BASE);
-	size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL,
-			  (uchar *) CFG_SDRAM_BASE);
+	size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
+			  (uchar *) CONFIG_SYS_SDRAM_BASE);
+	size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR2_9COL,
+			  (uchar *) CONFIG_SYS_SDRAM_BASE);
 
 	if (size8 < size9) {
 		psize = size9;
 		printf ("(60x:9COL) ");
 	} else {
-		psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
-				  (uchar *) CFG_SDRAM_BASE);
+		psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
+				  (uchar *) CONFIG_SYS_SDRAM_BASE);
 		printf ("(60x:8COL) ");
 	}
 
-#endif	/* CFG_RAMBOOT */
+#endif	/* CONFIG_SYS_RAMBOOT */
 
 	icache_enable ();
 
 	return (psize);
 }
 
-#if (CONFIG_COMMANDS & CFG_CMD_DOC)
-extern void doc_probe (ulong physadr);
+#if defined(CONFIG_CMD_DOC)
 void doc_init (void)
 {
-	doc_probe (CFG_DOC_BASE);
+	doc_probe (CONFIG_SYS_DOC_BASE);
 }
 #endif