X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=board%2Famcc%2Fyucca%2Fyucca.c;h=6608893651b22727b713b983d1f3d79268b527d8;hb=b77cddc7b52acd4ed78830ac681a398dd3053938;hp=90eaab1c80befc58c2ffa5ee782df9095a4640c4;hpb=cd84528f203a28f73e09c11e2737218938eaf71b;p=platform%2Fkernel%2Fu-boot.git diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c index 90eaab1..6608893 100644 --- a/board/amcc/yucca/yucca.c +++ b/board/amcc/yucca/yucca.c @@ -27,27 +27,17 @@ #include #include -#include #include -#include +#include +#include +#include #include "yucca.h" -#include "../cpu/ppc4xx/440spe_pcie.h" -#undef PCIE_ENDPOINT -/* #define PCIE_ENDPOINT 1 */ +DECLARE_GLOBAL_DATA_PTR; void fpga_init (void); -void get_sys_info(PPC440_SYS_INFO *board_cfg ); -int compare_to_true(char *str ); -char *remove_l_w_space(char *in_str ); -char *remove_t_w_space(char *in_str ); -int get_console_port(void); - -int ppc440spe_init_pcie_rootport(int port); -void ppc440spe_setup_pcie(struct pci_controller *hose, int port); - #define DEBUG_ENV #ifdef DEBUG_ENV #define DEBUGF(fmt,args...) printf(fmt ,##args) @@ -539,10 +529,10 @@ int board_early_init_f (void) mtdcr (uic0sr, 0x00000000); /* clear all interrupts */ mtdcr (uic0sr, 0xffffffff); /* clear all interrupts */ - /* SDR0_MFR should be part of Ethernet init */ - mfsdr (sdr_mfr, mfr); - mfr &= ~SDR0_MFR_ECS_MASK; - /*mtsdr(sdr_mfr, mfr);*/ + mfsdr(sdr_mfr, mfr); + mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */ + mtsdr(sdr_mfr, mfr); + fpga_init(); return 0; @@ -562,35 +552,39 @@ int checkboard (void) return 0; } -#if defined(CFG_DRAM_TEST) -int testdram (void) +/* + * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with + * board specific values. + */ +static int ppc440spe_rev_a(void) { - uint *pstart = (uint *) 0x00000000; - uint *pend = (uint *) 0x08000000; - uint *p; + if ((get_pvr() == PVR_440SPe_6_RA) || (get_pvr() == PVR_440SPe_RA)) + return 1; + else + return 0; +} - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; +u32 ddr_wrdtr(u32 default_val) { + /* + * Yucca boards with 440SPe rev. A need a slightly different setup + * for the MCIF0_WRDTR register. + */ + if (ppc440spe_rev_a()) + return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_270_DEG_ADV); - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } + return default_val; +} - for (p = pstart; p < pend; p++) - *p = 0x55555555; +u32 ddr_clktr(u32 default_val) { + /* + * Yucca boards with 440SPe rev. A need a slightly different setup + * for the MCIF0_CLKTR register. + */ + if (ppc440spe_rev_a()) + return (SDRAM_CLKTR_CLKP_180_DEG_ADV); - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - return 0; + return default_val; } -#endif /************************************************************************* * pci_pre_init @@ -604,7 +598,7 @@ int testdram (void) * certain pre-initialization actions. * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) +#if defined(CONFIG_PCI) int pci_pre_init(struct pci_controller * hose ) { unsigned long strap; @@ -621,7 +615,7 @@ int pci_pre_init(struct pci_controller * hose ) return 1; } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ +#endif /* defined(CONFIG_PCI) */ /************************************************************************* * pci_target_init @@ -634,8 +628,6 @@ int pci_pre_init(struct pci_controller * hose ) #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) void pci_target_init(struct pci_controller * hose ) { - DECLARE_GLOBAL_DATA_PTR; - /*-------------------------------------------------------------------+ * Disable everything *-------------------------------------------------------------------*/ @@ -715,27 +707,27 @@ void yucca_setup_pcie_fpga_rootpoint(int port) case 0: rootpoint = FPGA_REG1C_PE0_ROOTPOINT; endpoint = 0; - power = FPGA_REG1A_PE0_PWRON; + power = FPGA_REG1A_PE0_PWRON; green_led = FPGA_REG1A_PE0_GLED; - clock = FPGA_REG1A_PE0_REFCLK_ENABLE; + clock = FPGA_REG1A_PE0_REFCLK_ENABLE; yellow_led = FPGA_REG1A_PE0_YLED; reset_off = FPGA_REG1C_PE0_PERST; break; case 1: rootpoint = 0; endpoint = FPGA_REG1C_PE1_ENDPOINT; - power = FPGA_REG1A_PE1_PWRON; + power = FPGA_REG1A_PE1_PWRON; green_led = FPGA_REG1A_PE1_GLED; - clock = FPGA_REG1A_PE1_REFCLK_ENABLE; + clock = FPGA_REG1A_PE1_REFCLK_ENABLE; yellow_led = FPGA_REG1A_PE1_YLED; reset_off = FPGA_REG1C_PE1_PERST; break; case 2: rootpoint = 0; endpoint = FPGA_REG1C_PE2_ENDPOINT; - power = FPGA_REG1A_PE2_PWRON; + power = FPGA_REG1A_PE2_PWRON; green_led = FPGA_REG1A_PE2_GLED; - clock = FPGA_REG1A_PE2_REFCLK_ENABLE; + clock = FPGA_REG1A_PE2_REFCLK_ENABLE; yellow_led = FPGA_REG1A_PE2_YLED; reset_off = FPGA_REG1C_PE2_PERST; break; @@ -772,27 +764,27 @@ void yucca_setup_pcie_fpga_endpoint(int port) case 0: rootpoint = FPGA_REG1C_PE0_ROOTPOINT; endpoint = 0; - power = FPGA_REG1A_PE0_PWRON; + power = FPGA_REG1A_PE0_PWRON; green_led = FPGA_REG1A_PE0_GLED; - clock = FPGA_REG1A_PE0_REFCLK_ENABLE; + clock = FPGA_REG1A_PE0_REFCLK_ENABLE; yellow_led = FPGA_REG1A_PE0_YLED; reset_off = FPGA_REG1C_PE0_PERST; break; case 1: rootpoint = 0; endpoint = FPGA_REG1C_PE1_ENDPOINT; - power = FPGA_REG1A_PE1_PWRON; + power = FPGA_REG1A_PE1_PWRON; green_led = FPGA_REG1A_PE1_GLED; - clock = FPGA_REG1A_PE1_REFCLK_ENABLE; + clock = FPGA_REG1A_PE1_REFCLK_ENABLE; yellow_led = FPGA_REG1A_PE1_YLED; reset_off = FPGA_REG1C_PE1_PERST; break; case 2: rootpoint = 0; endpoint = FPGA_REG1C_PE2_ENDPOINT; - power = FPGA_REG1A_PE2_PWRON; + power = FPGA_REG1A_PE2_PWRON; green_led = FPGA_REG1A_PE2_GLED; - clock = FPGA_REG1A_PE2_REFCLK_ENABLE; + clock = FPGA_REG1A_PE2_REFCLK_ENABLE; yellow_led = FPGA_REG1A_PE2_YLED; reset_off = FPGA_REG1C_PE2_PERST; break; @@ -812,60 +804,74 @@ void yucca_setup_pcie_fpga_endpoint(int port) static struct pci_controller pcie_hose[3] = {{0},{0},{0}}; -void pcie_setup_hoses(void) +void pcie_setup_hoses(int busno) { struct pci_controller *hose; int i, bus; + int ret = 0; + char *env; + unsigned int delay; /* * assume we're called after the PCIX hose is initialized, which takes * bus ID 0 and therefore start numbering PCIe's from 1. */ - bus = 1; + bus = busno; for (i = 0; i <= 2; i++) { /* Check for yucca card presence */ if (!yucca_pcie_card_present(i)) continue; -#ifdef PCIE_ENDPOINT - yucca_setup_pcie_fpga_endpoint(i); - if (ppc440spe_init_pcie_endport(i)) { -#else - yucca_setup_pcie_fpga_rootpoint(i); - if (ppc440spe_init_pcie_rootport(i)) { -#endif - printf("PCIE%d: initialization failed\n", i); + if (is_end_point(i)) { + yucca_setup_pcie_fpga_endpoint(i); + ret = ppc4xx_init_pcie_endport(i); + } else { + yucca_setup_pcie_fpga_rootpoint(i); + ret = ppc4xx_init_pcie_rootport(i); + } + if (ret) { + printf("PCIE%d: initialization as %s failed\n", i, + is_end_point(i) ? "endpoint" : "root-complex"); continue; } hose = &pcie_hose[i]; hose->first_busno = bus; - hose->last_busno = bus; - bus++; + hose->last_busno = bus; + hose->current_busno = bus; /* setup mem resource */ pci_set_region(hose->regions + 0, CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE, CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE, CFG_PCIE_MEMSIZE, - PCI_REGION_MEM - ); + PCI_REGION_MEM); hose->region_count = 1; pci_register_hose(hose); -#ifdef PCIE_ENDPOINT - ppc440spe_setup_pcie_endpoint(hose, i); - /* - * Reson for no scanning is endpoint can not generate - * upstream configuration accesses. - */ -#else - ppc440spe_setup_pcie_rootpoint(hose, i); - /* - * Config access can only go down stream - */ - hose->last_busno = pci_hose_scan(hose); -#endif + if (is_end_point(i)) { + ppc4xx_setup_pcie_endpoint(hose, i); + /* + * Reson for no scanning is endpoint can not generate + * upstream configuration accesses. + */ + } else { + ppc4xx_setup_pcie_rootpoint(hose, i); + env = getenv("pciscandelay"); + if (env != NULL) { + delay = simple_strtoul(env, NULL, 10); + if (delay > 5) + printf("Warning, expect noticable delay before " + "PCIe scan due to 'pciscandelay' value!\n"); + mdelay(delay * 1000); + } + + /* + * Config access can only go down stream + */ + hose->last_busno = pci_hose_scan(hose); + bus = hose->last_busno + 1; + } } } #endif /* defined(CONFIG_PCI) */