X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=board%2Famcc%2Fyucca%2Fyucca.c;h=649315581a21181868f86126c71acfe8ef4e2e1b;hb=b0b867462c569e7accd6f78c942cbab028116ecf;hp=11d1743355c7fc7e81ae275f9731a48105b7e4bd;hpb=53677ef18e25c97ac613349087c5cb33ae5a2741;p=platform%2Fkernel%2Fu-boot.git diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c index 11d1743..6493155 100644 --- a/board/amcc/yucca/yucca.c +++ b/board/amcc/yucca/yucca.c @@ -28,9 +28,11 @@ #include #include #include +#include #include #include #include +#include #include "yucca.h" @@ -166,7 +168,7 @@ int board_early_init_f (void) | 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000 | +-------------------------------------------------------------------*/ - mtebc(xbcfg, EBC_CFG_LE_UNLOCK | + mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_16PERCLK | EBC_CFG_ATC_PREVIOUS | @@ -187,8 +189,8 @@ int board_early_init_f (void) | boot type | +-------------------------------------------------------------------*/ - mtebc(pb1ap, EBC_BXAP_FPGA); - mtebc(pb1cr, EBC_BXCR_FPGA_CS1); + mtebc(PB1AP, EBC_BXAP_FPGA); + mtebc(PB1CR, EBC_BXCR_FPGA_CS1); /*-------------------------------------------------------------------+ | @@ -333,10 +335,10 @@ int board_early_init_f (void) break; } - mtebc(pb0ap, ebc0_cs0_bxap_value); - mtebc(pb0cr, ebc0_cs0_bxcr_value); - mtebc(pb2ap, ebc0_cs2_bxap_value); - mtebc(pb2cr, ebc0_cs2_bxcr_value); + mtebc(PB0AP, ebc0_cs0_bxap_value); + mtebc(PB0CR, ebc0_cs0_bxcr_value); + mtebc(PB2AP, ebc0_cs2_bxap_value); + mtebc(PB2CR, ebc0_cs2_bxcr_value); /*--------------------------------------------------------------------+ | Interrupt controller setup for the AMCC 440SPe Evaluation board. @@ -484,54 +486,54 @@ int board_early_init_f (void) | interrupt trigger levels. Make bit 0 High priority. Clear all | interrupts again. +-------------------------------------------------------------------*/ - mtdcr (uic3sr, 0xffffffff); /* Clear all interrupts */ - mtdcr (uic3er, 0x00000000); /* disable all interrupts */ - mtdcr (uic3cr, 0x00000000); /* Set Critical / Non Critical + mtdcr (UIC3SR, 0xffffffff); /* Clear all interrupts */ + mtdcr (UIC3ER, 0x00000000); /* disable all interrupts */ + mtdcr (UIC3CR, 0x00000000); /* Set Critical / Non Critical * interrupts */ - mtdcr (uic3pr, 0xffffffff); /* Set Interrupt Polarities */ - mtdcr (uic3tr, 0x001fffff); /* Set Interrupt Trigger Levels */ - mtdcr (uic3vr, 0x00000001); /* Set Vect base=0,INT31 Highest + mtdcr (UIC3PR, 0xffffffff); /* Set Interrupt Polarities */ + mtdcr (UIC3TR, 0x001fffff); /* Set Interrupt Trigger Levels */ + mtdcr (UIC3VR, 0x00000001); /* Set Vect base=0,INT31 Highest * priority */ - mtdcr (uic3sr, 0x00000000); /* clear all interrupts */ - mtdcr (uic3sr, 0xffffffff); /* clear all interrupts */ + mtdcr (UIC3SR, 0x00000000); /* clear all interrupts */ + mtdcr (UIC3SR, 0xffffffff); /* clear all interrupts */ - mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */ - mtdcr (uic2er, 0x00000000); /* disable all interrupts */ - mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical + mtdcr (UIC2SR, 0xffffffff); /* Clear all interrupts */ + mtdcr (UIC2ER, 0x00000000); /* disable all interrupts */ + mtdcr (UIC2CR, 0x00000000); /* Set Critical / Non Critical * interrupts */ - mtdcr (uic2pr, 0xebebebff); /* Set Interrupt Polarities */ - mtdcr (uic2tr, 0x74747400); /* Set Interrupt Trigger Levels */ - mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest + mtdcr (UIC2PR, 0xebebebff); /* Set Interrupt Polarities */ + mtdcr (UIC2TR, 0x74747400); /* Set Interrupt Trigger Levels */ + mtdcr (UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest * priority */ - mtdcr (uic2sr, 0x00000000); /* clear all interrupts */ - mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */ + mtdcr (UIC2SR, 0x00000000); /* clear all interrupts */ + mtdcr (UIC2SR, 0xffffffff); /* clear all interrupts */ - mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts */ - mtdcr (uic1er, 0x00000000); /* disable all interrupts */ - mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical + mtdcr (UIC1SR, 0xffffffff); /* Clear all interrupts */ + mtdcr (UIC1ER, 0x00000000); /* disable all interrupts */ + mtdcr (UIC1CR, 0x00000000); /* Set Critical / Non Critical * interrupts */ - mtdcr (uic1pr, 0xffffffff); /* Set Interrupt Polarities */ - mtdcr (uic1tr, 0x001f8040); /* Set Interrupt Trigger Levels */ - mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest + mtdcr (UIC1PR, 0xffffffff); /* Set Interrupt Polarities */ + mtdcr (UIC1TR, 0x001f8040); /* Set Interrupt Trigger Levels */ + mtdcr (UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest * priority */ - mtdcr (uic1sr, 0x00000000); /* clear all interrupts */ - mtdcr (uic1sr, 0xffffffff); /* clear all interrupts */ + mtdcr (UIC1SR, 0x00000000); /* clear all interrupts */ + mtdcr (UIC1SR, 0xffffffff); /* clear all interrupts */ - mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */ - mtdcr (uic0er, 0x00000000); /* disable all interrupts excepted + mtdcr (UIC0SR, 0xffffffff); /* Clear all interrupts */ + mtdcr (UIC0ER, 0x00000000); /* disable all interrupts excepted * cascade to be checked */ - mtdcr (uic0cr, 0x00104001); /* Set Critical / Non Critical + mtdcr (UIC0CR, 0x00104001); /* Set Critical / Non Critical * interrupts */ - mtdcr (uic0pr, 0xffffffff); /* Set Interrupt Polarities */ - mtdcr (uic0tr, 0x010f0004); /* Set Interrupt Trigger Levels */ - mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest + mtdcr (UIC0PR, 0xffffffff); /* Set Interrupt Polarities */ + mtdcr (UIC0TR, 0x010f0004); /* Set Interrupt Trigger Levels */ + mtdcr (UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest * priority */ - mtdcr (uic0sr, 0x00000000); /* clear all interrupts */ - mtdcr (uic0sr, 0xffffffff); /* clear all interrupts */ + mtdcr (UIC0SR, 0x00000000); /* clear all interrupts */ + mtdcr (UIC0SR, 0xffffffff); /* clear all interrupts */ - mfsdr(sdr_mfr, mfr); + mfsdr(SDR0_MFR, mfr); mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */ - mtsdr(sdr_mfr, mfr); + mtsdr(SDR0_MFR, mfr); fpga_init(); @@ -586,36 +588,6 @@ u32 ddr_clktr(u32 default_val) { return default_val; } -#if defined(CFG_DRAM_TEST) -int testdram (void) -{ - uint *pstart = (uint *) 0x00000000; - uint *pend = (uint *) 0x08000000; - uint *p; - - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - return 0; -} -#endif - /************************************************************************* * pci_pre_init * @@ -637,7 +609,7 @@ int pci_pre_init(struct pci_controller * hose ) * The yucca board is always configured as the host & requires the * PCI arbiter to be enabled. *-------------------------------------------------------------------*/ - mfsdr(sdr_sdstp1, strap); + mfsdr(SDR0_SDSTP1, strap); if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) { printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap); return 0; @@ -655,35 +627,35 @@ int pci_pre_init(struct pci_controller * hose ) * may not be sufficient for a given board. * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) +#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) void pci_target_init(struct pci_controller * hose ) { /*-------------------------------------------------------------------+ * Disable everything *-------------------------------------------------------------------*/ - out32r( PCIX0_PIM0SA, 0 ); /* disable */ - out32r( PCIX0_PIM1SA, 0 ); /* disable */ - out32r( PCIX0_PIM2SA, 0 ); /* disable */ - out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */ + out32r( PCIL0_PIM0SA, 0 ); /* disable */ + out32r( PCIL0_PIM1SA, 0 ); /* disable */ + out32r( PCIL0_PIM2SA, 0 ); /* disable */ + out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */ /*-------------------------------------------------------------------+ * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 * strapping options to not support sizes such as 128/256 MB. *-------------------------------------------------------------------*/ - out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE ); - out32r( PCIX0_PIM0LAH, 0 ); - out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 ); - out32r( PCIX0_BAR0, 0 ); + out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE ); + out32r( PCIL0_PIM0LAH, 0 ); + out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 ); + out32r( PCIL0_BAR0, 0 ); /*-------------------------------------------------------------------+ * Program the board's subsystem id/vendor id *-------------------------------------------------------------------*/ - out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID ); - out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID ); + out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); + out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID ); - out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY ); + out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY ); } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ +#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ #if defined(CONFIG_PCI) /************************************************************************* @@ -707,7 +679,7 @@ int is_pci_host(struct pci_controller *hose) return 1; } -int yucca_pcie_card_present(int port) +int board_pcie_card_present(int port) { u16 reg; @@ -725,183 +697,54 @@ int yucca_pcie_card_present(int port) } /* - * For the given slot, set rootpoint mode, send power to the slot, - * turn on the green LED and turn off the yellow LED, enable the clock - * and turn off reset. - */ -void yucca_setup_pcie_fpga_rootpoint(int port) -{ - u16 power, clock, green_led, yellow_led, reset_off, rootpoint, endpoint; - - switch(port) { - case 0: - rootpoint = FPGA_REG1C_PE0_ROOTPOINT; - endpoint = 0; - power = FPGA_REG1A_PE0_PWRON; - green_led = FPGA_REG1A_PE0_GLED; - clock = FPGA_REG1A_PE0_REFCLK_ENABLE; - yellow_led = FPGA_REG1A_PE0_YLED; - reset_off = FPGA_REG1C_PE0_PERST; - break; - case 1: - rootpoint = 0; - endpoint = FPGA_REG1C_PE1_ENDPOINT; - power = FPGA_REG1A_PE1_PWRON; - green_led = FPGA_REG1A_PE1_GLED; - clock = FPGA_REG1A_PE1_REFCLK_ENABLE; - yellow_led = FPGA_REG1A_PE1_YLED; - reset_off = FPGA_REG1C_PE1_PERST; - break; - case 2: - rootpoint = 0; - endpoint = FPGA_REG1C_PE2_ENDPOINT; - power = FPGA_REG1A_PE2_PWRON; - green_led = FPGA_REG1A_PE2_GLED; - clock = FPGA_REG1A_PE2_REFCLK_ENABLE; - yellow_led = FPGA_REG1A_PE2_YLED; - reset_off = FPGA_REG1C_PE2_PERST; - break; - - default: - return; - } - - out_be16((u16 *)FPGA_REG1A, - ~(power | clock | green_led) & - (yellow_led | in_be16((u16 *)FPGA_REG1A))); - - out_be16((u16 *)FPGA_REG1C, - ~(endpoint | reset_off) & - (rootpoint | in_be16((u16 *)FPGA_REG1C))); - /* - * Leave device in reset for a while after powering on the - * slot to give it a chance to initialize. - */ - udelay(250 * 1000); - - out_be16((u16 *)FPGA_REG1C, reset_off | in_be16((u16 *)FPGA_REG1C)); -} -/* * For the given slot, set endpoint mode, send power to the slot, - * turn on the green LED and turn off the yellow LED, enable the clock - * .In end point mode reset bit is read only. + * turn on the green LED and turn off the yellow LED, enable the + * clock. In end point mode reset bit is read only. */ -void yucca_setup_pcie_fpga_endpoint(int port) +void board_pcie_setup_port(int port, int rootpoint) { - u16 power, clock, green_led, yellow_led, reset_off, rootpoint, endpoint; + u16 power, clock, green_led, yellow_led, + reset_off, rp, ep; - switch(port) { + switch (port) { case 0: - rootpoint = FPGA_REG1C_PE0_ROOTPOINT; - endpoint = 0; - power = FPGA_REG1A_PE0_PWRON; - green_led = FPGA_REG1A_PE0_GLED; - clock = FPGA_REG1A_PE0_REFCLK_ENABLE; - yellow_led = FPGA_REG1A_PE0_YLED; - reset_off = FPGA_REG1C_PE0_PERST; + rp = FPGA_REG1C_PE0_ROOTPOINT; + ep = 0; break; case 1: - rootpoint = 0; - endpoint = FPGA_REG1C_PE1_ENDPOINT; - power = FPGA_REG1A_PE1_PWRON; - green_led = FPGA_REG1A_PE1_GLED; - clock = FPGA_REG1A_PE1_REFCLK_ENABLE; - yellow_led = FPGA_REG1A_PE1_YLED; - reset_off = FPGA_REG1C_PE1_PERST; + rp = 0; + ep = FPGA_REG1C_PE1_ENDPOINT; break; case 2: - rootpoint = 0; - endpoint = FPGA_REG1C_PE2_ENDPOINT; - power = FPGA_REG1A_PE2_PWRON; - green_led = FPGA_REG1A_PE2_GLED; - clock = FPGA_REG1A_PE2_REFCLK_ENABLE; - yellow_led = FPGA_REG1A_PE2_YLED; - reset_off = FPGA_REG1C_PE2_PERST; + rp = 0; + ep = FPGA_REG1C_PE2_ENDPOINT; break; default: return; } - out_be16((u16 *)FPGA_REG1A, - ~(power | clock | green_led) & - (yellow_led | in_be16((u16 *)FPGA_REG1A))); - - out_be16((u16 *)FPGA_REG1C, - ~(rootpoint | reset_off) & - (endpoint | in_be16((u16 *)FPGA_REG1C))); -} + power = FPGA_REG1A_PWRON_ENCODE(port); + green_led = FPGA_REG1A_GLED_ENCODE(port); + clock = FPGA_REG1A_REFCLK_ENCODE(port); + yellow_led = FPGA_REG1A_YLED_ENCODE(port); + reset_off = FPGA_REG1C_PERST_ENCODE(port); -static struct pci_controller pcie_hose[3] = {{0},{0},{0}}; + out_be16((u16 *)FPGA_REG1A, ~(power | clock | green_led) & + (yellow_led | in_be16((u16 *)FPGA_REG1A))); -void pcie_setup_hoses(int busno) -{ - struct pci_controller *hose; - int i, bus; - int ret = 0; - char *env; - unsigned int delay; + out_be16((u16 *)FPGA_REG1C, ~(ep | reset_off) & + (rp | in_be16((u16 *)FPGA_REG1C))); - /* - * assume we're called after the PCIX hose is initialized, which takes - * bus ID 0 and therefore start numbering PCIe's from 1. - */ - bus = busno; - for (i = 0; i <= 2; i++) { - /* Check for yucca card presence */ - if (!yucca_pcie_card_present(i)) - continue; - - if (is_end_point(i)) { - yucca_setup_pcie_fpga_endpoint(i); - ret = ppc4xx_init_pcie_endport(i); - } else { - yucca_setup_pcie_fpga_rootpoint(i); - ret = ppc4xx_init_pcie_rootport(i); - } - if (ret) { - printf("PCIE%d: initialization as %s failed\n", i, - is_end_point(i) ? "endpoint" : "root-complex"); - continue; - } - - hose = &pcie_hose[i]; - hose->first_busno = bus; - hose->last_busno = bus; - hose->current_busno = bus; - - /* setup mem resource */ - pci_set_region(hose->regions + 0, - CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE, - CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE, - CFG_PCIE_MEMSIZE, - PCI_REGION_MEM); - hose->region_count = 1; - pci_register_hose(hose); - - if (is_end_point(i)) { - ppc4xx_setup_pcie_endpoint(hose, i); - /* - * Reson for no scanning is endpoint can not generate - * upstream configuration accesses. - */ - } else { - ppc4xx_setup_pcie_rootpoint(hose, i); - env = getenv("pciscandelay"); - if (env != NULL) { - delay = simple_strtoul(env, NULL, 10); - if (delay > 5) - printf("Warning, expect noticable delay before " - "PCIe scan due to 'pciscandelay' value!\n"); - mdelay(delay * 1000); - } + if (rootpoint) { + /* + * Leave device in reset for a while after powering on the + * slot to give it a chance to initialize. + */ + udelay(250 * 1000); - /* - * Config access can only go down stream - */ - hose->last_busno = pci_hose_scan(hose); - bus = hose->last_busno + 1; - } + out_be16((u16 *)FPGA_REG1C, + reset_off | in_be16((u16 *)FPGA_REG1C)); } } #endif /* defined(CONFIG_PCI) */ @@ -909,10 +752,6 @@ void pcie_setup_hoses(int busno) int misc_init_f (void) { uint reg; -#if defined(CONFIG_STRESS) - uint i ; - uint disp; -#endif out16(FPGA_REG10, (in16(FPGA_REG10) & ~(FPGA_REG10_AUTO_NEG_DIS|FPGA_REG10_RESET_ETH)) | @@ -927,67 +766,23 @@ int misc_init_f (void) /* minimal init for PCIe */ /* pci express 0 Endpoint Mode */ - mfsdr(SDR0_PE0DLPSET, reg); + mfsdr(SDRN_PESDR_DLPSET(0), reg); reg &= (~0x00400000); - mtsdr(SDR0_PE0DLPSET, reg); + mtsdr(SDRN_PESDR_DLPSET(0), reg); /* pci express 1 Rootpoint Mode */ - mfsdr(SDR0_PE1DLPSET, reg); + mfsdr(SDRN_PESDR_DLPSET(1), reg); reg |= 0x00400000; - mtsdr(SDR0_PE1DLPSET, reg); + mtsdr(SDRN_PESDR_DLPSET(1), reg); /* pci express 2 Rootpoint Mode */ - mfsdr(SDR0_PE2DLPSET, reg); + mfsdr(SDRN_PESDR_DLPSET(2), reg); reg |= 0x00400000; - mtsdr(SDR0_PE2DLPSET, reg); + mtsdr(SDRN_PESDR_DLPSET(2), reg); out16(FPGA_REG1C,(in16 (FPGA_REG1C) & ~FPGA_REG1C_PE0_ROOTPOINT & ~FPGA_REG1C_PE1_ENDPOINT & ~FPGA_REG1C_PE2_ENDPOINT)); -#if defined(CONFIG_STRESS) - /* - * all this setting done by linux only needed by stress an charac. test - * procedure - * PCIe 1 Rootpoint PCIe2 Endpoint - * PCIe 0 FIR Pre-emphasis Filter Coefficients & Transmit Driver - * Power Level - */ - for (i = 0, disp = 0; i < 8; i++, disp += 3) { - mfsdr(SDR0_PE0HSSSET1L0 + disp, reg); - reg |= 0x33000000; - mtsdr(SDR0_PE0HSSSET1L0 + disp, reg); - } - - /* - * PCIe 1 FIR Pre-emphasis Filter Coefficients & Transmit Driver - * Power Level - */ - for (i = 0, disp = 0; i < 4; i++, disp += 3) { - mfsdr(SDR0_PE1HSSSET1L0 + disp, reg); - reg |= 0x33000000; - mtsdr(SDR0_PE1HSSSET1L0 + disp, reg); - } - - /* - * PCIE 2 FIR Pre-emphasis Filter Coefficients & Transmit Driver - * Power Level - */ - for (i = 0, disp = 0; i < 4; i++, disp += 3) { - mfsdr(SDR0_PE2HSSSET1L0 + disp, reg); - reg |= 0x33000000; - mtsdr(SDR0_PE2HSSSET1L0 + disp, reg); - } - - reg = 0x21242222; - mtsdr(SDR0_PE2UTLSET1, reg); - reg = 0x11000000; - mtsdr(SDR0_PE2UTLSET2, reg); - /* pci express 1 Endpoint Mode */ - reg = 0x00004000; - mtsdr(SDR0_PE2DLPSET, reg); - - mtsdr(SDR0_UART1, 0x2080005a); /* patch for TG */ -#endif return 0; } @@ -1030,3 +825,9 @@ int onboard_pci_arbiter_selected(int core_pci) #endif return (BOARD_OPTION_NOT_SELECTED); } + +int board_eth_init(bd_t *bis) +{ + cpu_eth_init(bis); + return pci_eth_init(bis); +}