X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=board%2Famcc%2Fsequoia%2Fsdram.c;h=9bedb5bc8e3ba1eccb63ef8c52d7e075e69d55fd;hb=04735a8fc45ba7c9f5b17d4837a0c649087b29e1;hp=2c5a21806a31cd6072d45c464c425cde77a87f0e;hpb=3be2bdf5dc69b3142c1162a59bc67191c9077567;p=platform%2Fkernel%2Fu-boot.git

diff --git a/board/amcc/sequoia/sdram.c b/board/amcc/sequoia/sdram.c
index 2c5a218..9bedb5b 100644
--- a/board/amcc/sequoia/sdram.c
+++ b/board/amcc/sequoia/sdram.c
@@ -20,29 +20,22 @@
 #include <asm/io.h>
 #include <asm/ppc440.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /*-----------------------------------------------------------------------------+
  * Prototypes
  *-----------------------------------------------------------------------------*/
 extern int denali_wait_for_dlllock(void);
 extern void denali_core_search_data_eye(void);
 
-#if defined(CONFIG_NAND_SPL)
-/* Using arch/powerpc/cpu/ppc4xx/speed.c to calculate the bus frequency is too big
- * for the 4k NAND boot image so define bus_frequency to 133MHz here
- * which is save for the refresh counter setup.
- */
-#define get_bus_freq(val)	133333333
-#endif
-
 /*************************************************************************
  *
  * initdram -- 440EPx's DDR controller is a DENALI Core
  *
  ************************************************************************/
-phys_size_t initdram (int board_type)
+int initdram(void)
 {
-#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT)) || \
-    defined(CONFIG_NAND_SPL)
+#if !defined(CONFIG_SYS_RAMBOOT)
 	ulong speed = get_bus_freq(0);
 
 	mtsdram(DDR0_02, 0x00000000);
@@ -81,7 +74,7 @@ phys_size_t initdram (int board_type)
 	mtsdram(DDR0_02, 0x00000001);
 
 	denali_wait_for_dlllock();
-#endif /* #ifndef CONFIG_NAND_U_BOOT */
+#endif /* #ifndef CONFIG_SYS_RAMBOOT */
 
 #ifdef CONFIG_DDR_DATA_EYE
 	/* -----------------------------------------------------------+
@@ -97,5 +90,7 @@ phys_size_t initdram (int board_type)
 	 */
 	set_mcsr(get_mcsr());
 
-	return (CONFIG_SYS_MBYTES_SDRAM << 20);
+	gd->ram_size = CONFIG_SYS_MBYTES_SDRAM << 20;
+
+	return 0;
 }