X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=board%2Famcc%2Focotea%2Focotea.c;h=7bffa3c4082f772a3b8f904cab15072040320aed;hb=35e3717772c8c3534c18d8aac69e4b822777c23b;hp=4d1d093219eb1972f1712ba733bdd8a06fae0c28;hpb=5de851403b01489b493fa83137ad990b8ce60d1c;p=platform%2Fkernel%2Fu-boot.git diff --git a/board/amcc/ocotea/ocotea.c b/board/amcc/ocotea/ocotea.c index 4d1d093..7bffa3c 100644 --- a/board/amcc/ocotea/ocotea.c +++ b/board/amcc/ocotea/ocotea.c @@ -42,7 +42,7 @@ void fpga_init (void); int board_early_init_f (void) { unsigned long mfr; - unsigned char *fpga_base = (unsigned char *) CFG_FPGA_BASE; + unsigned char *fpga_base = (unsigned char *) CONFIG_SYS_FPGA_BASE; unsigned char switch_status; unsigned long cs0_base; unsigned long cs0_size; @@ -54,7 +54,7 @@ int board_early_init_f (void) /*-------------------------------------------------------------------------+ | Initialize EBC CONFIG +-------------------------------------------------------------------------*/ - mtebc(xbcfg, EBC_CFG_LE_UNLOCK | + mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT | @@ -63,14 +63,14 @@ int board_early_init_f (void) /*-------------------------------------------------------------------------+ | FPGA. Initialize bank 7 with default values. +-------------------------------------------------------------------------*/ - mtebc(pb7ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)| + mtebc(PB7AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)| EBC_BXAP_BCE_DISABLE| EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED| EBC_BXAP_BEM_WRITEONLY| EBC_BXAP_PEN_DISABLED); - mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48300000)| + mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48300000)| EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); /* read FPGA base register FPGA_REG0 */ @@ -95,53 +95,53 @@ int board_early_init_f (void) /*-------------------------------------------------------------------------+ | 1 MB FLASH / 1 MB SRAM. Initialize bank 0 with default values. +-------------------------------------------------------------------------*/ - mtebc(pb0ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs0_twt)| + mtebc(PB0AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs0_twt)| EBC_BXAP_BCE_DISABLE| EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED| EBC_BXAP_BEM_WRITEONLY| EBC_BXAP_PEN_DISABLED); - mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(cs0_base)| + mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(cs0_base)| cs0_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); /*-------------------------------------------------------------------------+ | 8KB NVRAM/RTC. Initialize bank 1 with default values. +-------------------------------------------------------------------------*/ - mtebc(pb1ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(10)| + mtebc(PB1AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(10)| EBC_BXAP_BCE_DISABLE| EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED| EBC_BXAP_BEM_WRITEONLY| EBC_BXAP_PEN_DISABLED); - mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000)| + mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x48000000)| EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); /*-------------------------------------------------------------------------+ | 4 MB FLASH. Initialize bank 2 with default values. +-------------------------------------------------------------------------*/ - mtebc(pb2ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs2_twt)| + mtebc(PB2AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs2_twt)| EBC_BXAP_BCE_DISABLE| EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED| EBC_BXAP_BEM_WRITEONLY| EBC_BXAP_PEN_DISABLED); - mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(cs2_base)| + mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(cs2_base)| cs2_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); /*-------------------------------------------------------------------------+ | FPGA. Initialize bank 7 with default values. +-------------------------------------------------------------------------*/ - mtebc(pb7ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)| + mtebc(PB7AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)| EBC_BXAP_BCE_DISABLE| EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED| EBC_BXAP_BEM_WRITEONLY| EBC_BXAP_PEN_DISABLED); - mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48300000)| + mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48300000)| EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); /*-------------------------------------------------------------------- @@ -159,39 +159,39 @@ int board_early_init_f (void) * UIC2 UIC1 * UIC3 UIC2 */ - mtdcr (uic1sr, 0xffffffff); /* clear all */ - mtdcr (uic1er, 0x00000000); /* disable all */ - mtdcr (uic1cr, 0x00000009); /* SMI & UIC1 crit are critical */ - mtdcr (uic1pr, 0xfffffe13); /* per ref-board manual */ - mtdcr (uic1tr, 0x01c00008); /* per ref-board manual */ - mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic1sr, 0xffffffff); /* clear all */ - - mtdcr (uic2sr, 0xffffffff); /* clear all */ - mtdcr (uic2er, 0x00000000); /* disable all */ - mtdcr (uic2cr, 0x00000000); /* all non-critical */ - mtdcr (uic2pr, 0xffffe0ff); /* per ref-board manual */ - mtdcr (uic2tr, 0x00ffc000); /* per ref-board manual */ - mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic2sr, 0xffffffff); /* clear all */ - - mtdcr (uic3sr, 0xffffffff); /* clear all */ - mtdcr (uic3er, 0x00000000); /* disable all */ - mtdcr (uic3cr, 0x00000000); /* all non-critical */ - mtdcr (uic3pr, 0xffffffff); /* per ref-board manual */ - mtdcr (uic3tr, 0x00ff8c0f); /* per ref-board manual */ - mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic3sr, 0xffffffff); /* clear all */ - - mtdcr (uic0sr, 0xfc000000); /* clear all */ - mtdcr (uic0er, 0x00000000); /* disable all */ - mtdcr (uic0cr, 0x00000000); /* all non-critical */ - mtdcr (uic0pr, 0xfc000000); /* */ - mtdcr (uic0tr, 0x00000000); /* */ - mtdcr (uic0vr, 0x00000001); /* */ - mfsdr (sdr_mfr, mfr); + mtdcr (UIC1SR, 0xffffffff); /* clear all */ + mtdcr (UIC1ER, 0x00000000); /* disable all */ + mtdcr (UIC1CR, 0x00000009); /* SMI & UIC1 crit are critical */ + mtdcr (UIC1PR, 0xfffffe13); /* per ref-board manual */ + mtdcr (UIC1TR, 0x01c00008); /* per ref-board manual */ + mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (UIC1SR, 0xffffffff); /* clear all */ + + mtdcr (UIC2SR, 0xffffffff); /* clear all */ + mtdcr (UIC2ER, 0x00000000); /* disable all */ + mtdcr (UIC2CR, 0x00000000); /* all non-critical */ + mtdcr (UIC2PR, 0xffffe0ff); /* per ref-board manual */ + mtdcr (UIC2TR, 0x00ffc000); /* per ref-board manual */ + mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (UIC2SR, 0xffffffff); /* clear all */ + + mtdcr (UIC3SR, 0xffffffff); /* clear all */ + mtdcr (UIC3ER, 0x00000000); /* disable all */ + mtdcr (UIC3CR, 0x00000000); /* all non-critical */ + mtdcr (UIC3PR, 0xffffffff); /* per ref-board manual */ + mtdcr (UIC3TR, 0x00ff8c0f); /* per ref-board manual */ + mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (UIC3SR, 0xffffffff); /* clear all */ + + mtdcr (UIC0SR, 0xfc000000); /* clear all */ + mtdcr (UIC0ER, 0x00000000); /* disable all */ + mtdcr (UIC0CR, 0x00000000); /* all non-critical */ + mtdcr (UIC0PR, 0xfc000000); /* */ + mtdcr (UIC0TR, 0x00000000); /* */ + mtdcr (UIC0VR, 0x00000001); /* */ + mfsdr (SDR0_MFR, mfr); mfr &= ~SDR0_MFR_ECS_MASK; -/* mtsdr(sdr_mfr, mfr); */ +/* mtsdr(SDR0_MFR, mfr); */ fpga_init(); return 0; @@ -241,11 +241,11 @@ long int fixed_sdram (void) /*-------------------------------------------------------------------- * Setup some default *------------------------------------------------------------------*/ - mtsdram (mem_uabba, 0x00000000); /* ubba=0 (default) */ - mtsdram (mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ - mtsdram (mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */ - mtsdram (mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */ - mtsdram (mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ + mtsdram (SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */ + mtsdram (SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ + mtsdram (SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */ + mtsdram (SDRAM0_WDDCTR, 0x00000000); /* wrcp=0 dcd=0 */ + mtsdram (SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ /*-------------------------------------------------------------------- * Setup for board-specific specific mem @@ -253,20 +253,20 @@ long int fixed_sdram (void) /* * Following for CAS Latency = 2.5 @ 133 MHz PLB */ - mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */ - mtsdram (mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */ + mtsdram (SDRAM0_B0CR, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */ + mtsdram (SDRAM0_TR0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */ /* RA=10 RD=3 */ - mtsdram (mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */ - mtsdram (mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */ - mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */ + mtsdram (SDRAM0_TR1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */ + mtsdram (SDRAM0_RTR, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */ + mtsdram (SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM */ udelay (400); /* Delay 200 usecs (min) */ /*-------------------------------------------------------------------- * Enable the controller, then wait for DCEN to complete *------------------------------------------------------------------*/ - mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */ + mtsdram (SDRAM0_CFG0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */ for (;;) { - mfsdram (mem_mcsts, reg); + mfsdram (SDRAM0_MCSTS, reg); if (reg & 0x80000000) break; } @@ -275,102 +275,6 @@ long int fixed_sdram (void) } #endif /* !defined(CONFIG_SPD_EEPROM) */ - -/************************************************************************* - * pci_pre_init - * - * This routine is called just prior to registering the hose and gives - * the board the opportunity to check things. Returning a value of zero - * indicates that things are bad & PCI initialization should be aborted. - * - * Different boards may wish to customize the pci controller structure - * (add regions, override default access routines, etc) or perform - * certain pre-initialization actions. - * - ************************************************************************/ -#if defined(CONFIG_PCI) -int pci_pre_init(struct pci_controller * hose ) -{ - unsigned long strap; - - /*--------------------------------------------------------------------------+ - * The ocotea board is always configured as the host & requires the - * PCI arbiter to be enabled. - *--------------------------------------------------------------------------*/ - mfsdr(sdr_sdstp1, strap); - if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){ - printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap); - return 0; - } - - return 1; -} -#endif /* defined(CONFIG_PCI) */ - -/************************************************************************* - * pci_target_init - * - * The bootstrap configuration provides default settings for the pci - * inbound map (PIM). But the bootstrap config choices are limited and - * may not be sufficient for a given board. - * - ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) -void pci_target_init(struct pci_controller * hose ) -{ - /*--------------------------------------------------------------------------+ - * Disable everything - *--------------------------------------------------------------------------*/ - out32r( PCIX0_PIM0SA, 0 ); /* disable */ - out32r( PCIX0_PIM1SA, 0 ); /* disable */ - out32r( PCIX0_PIM2SA, 0 ); /* disable */ - out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */ - - /*--------------------------------------------------------------------------+ - * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping - * options to not support sizes such as 128/256 MB. - *--------------------------------------------------------------------------*/ - out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE ); - out32r( PCIX0_PIM0LAH, 0 ); - out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 ); - - out32r( PCIX0_BAR0, 0 ); - - /*--------------------------------------------------------------------------+ - * Program the board's subsystem id/vendor id - *--------------------------------------------------------------------------*/ - out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID ); - out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID ); - - out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY ); -} -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ - - -/************************************************************************* - * is_pci_host - * - * This routine is called to determine if a pci scan should be - * performed. With various hardware environments (especially cPCI and - * PPMC) it's insufficient to depend on the state of the arbiter enable - * bit in the strap register, or generic host/adapter assumptions. - * - * Rather than hard-code a bad assumption in the general 440 code, the - * 440 pci code requires the board to decide at runtime. - * - * Return 0 for adapter mode, non-zero for host (monarch) mode. - * - * - ************************************************************************/ -#if defined(CONFIG_PCI) -int is_pci_host(struct pci_controller *hose) -{ - /* The ocotea board is always configured as host. */ - return(1); -} -#endif /* defined(CONFIG_PCI) */ - - void fpga_init(void) { unsigned long group; @@ -379,8 +283,8 @@ void fpga_init(void) unsigned long sdr0_cust0; unsigned long pvr; - mfsdr (sdr_pfc0, sdr0_pfc0); - mfsdr (sdr_pfc1, sdr0_pfc1); + mfsdr (SDR0_PFC0, sdr0_pfc0); + mfsdr (SDR0_PFC1, sdr0_pfc1); group = SDR0_PFC1_EPS_DECODE(sdr0_pfc1); pvr = get_pvr (); @@ -390,8 +294,8 @@ void fpga_init(void) sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS; out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) | FPGA_REG2_EXT_INTFACE_ENABLE); - mtsdr (sdr_pfc0, sdr0_pfc0); - mtsdr (sdr_pfc1, sdr0_pfc1); + mtsdr (SDR0_PFC0, sdr0_pfc0); + mtsdr (SDR0_PFC1, sdr0_pfc1); } else { sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_ENABLE; switch (group) @@ -403,8 +307,8 @@ void fpga_init(void) out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) | FPGA_REG2_EXT_INTFACE_ENABLE); sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS; - mtsdr (sdr_pfc0, sdr0_pfc0); - mtsdr (sdr_pfc1, sdr0_pfc1); + mtsdr (SDR0_PFC0, sdr0_pfc0); + mtsdr (SDR0_PFC1, sdr0_pfc1); break; case 3: case 4: @@ -412,8 +316,8 @@ void fpga_init(void) case 6: /* CPU trace B - Over EBMI */ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_CPUTRACE; - mtsdr (sdr_pfc0, sdr0_pfc0); - mtsdr (sdr_pfc1, sdr0_pfc1); + mtsdr (SDR0_PFC0, sdr0_pfc0); + mtsdr (SDR0_PFC1, sdr0_pfc1); out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) | FPGA_REG2_EXT_INTFACE_DISABLE); break; @@ -421,8 +325,8 @@ void fpga_init(void) } /* Initialize the ethernet specific functions in the fpga */ - mfsdr(sdr_pfc1, sdr0_pfc1); - mfsdr(sdr_cust0, sdr0_cust0); + mfsdr(SDR0_PFC1, sdr0_pfc1); + mfsdr(SDR0_CUST0, sdr0_cust0); if ( (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) == 4) && ((SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII) || (SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_TBI))) @@ -496,15 +400,3 @@ void fpga_init(void) return; } - -#ifdef CONFIG_POST -/* - * Returns 1 if keys pressed to start the power-on long-running tests - * Called from board_init_f(). - */ -int post_hotkeys_pressed(void) -{ - - return (ctrlc()); -} -#endif