X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=board%2Famcc%2Fluan%2Finit.S;h=7cca3191fdafafc33477529a05ba0d903bd439ac;hb=550650ddd0fde00f245bc3da72d7272844198394;hp=d5ee117dfaca2a6e713b0f01223ab1e8eab24924;hpb=fc1e45ce6e45d5d88a42f4245b2d7ee134270029;p=platform%2Fkernel%2Fu-boot.git

diff --git a/board/amcc/luan/init.S b/board/amcc/luan/init.S
index d5ee117..7cca319 100644
--- a/board/amcc/luan/init.S
+++ b/board/amcc/luan/init.S
@@ -25,7 +25,8 @@
 
 #include <ppc_asm.tmpl>
 #include <config.h>
-#include <asm-ppc/mmu.h>
+#include <asm/mmu.h>
+#include <asm/ppc4xx.h>
 
 /**************************************************************************
  * TLB TABLE
@@ -48,13 +49,13 @@ tlbtab:
 	 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
 	 * speed up boot process. It is patched after relocation to enable SA_I
 	 */
-	tlbentry(0xfff00000, SZ_1M, 0xfff00000, 1, AC_R|AC_W|AC_X|SA_G)
+	tlbentry(0xfff00000, SZ_1M, 0xfff00000, 1, AC_RWX | SA_G)
 
-	tlbentry(0xffc00000, SZ_1M, 0xffc00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
-	tlbentry(0xffd00000, SZ_1M, 0xffd00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
-	tlbentry(0xffe00000, SZ_1M, 0xffe00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
-	tlbentry(0xff900000, SZ_1M, 0xff900000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
-	tlbentry(CFG_EPLD_BASE, SZ_256K, 0xff000000, 1, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(0xffc00000, SZ_1M, 0xffc00000, 1, AC_RWX | SA_IG)
+	tlbentry(0xffd00000, SZ_1M, 0xffd00000, 1, AC_RWX | SA_IG)
+	tlbentry(0xffe00000, SZ_1M, 0xffe00000, 1, AC_RWX | SA_IG)
+	tlbentry(0xff900000, SZ_1M, 0xff900000, 1, AC_RWX | SA_IG)
+	tlbentry(CONFIG_SYS_EPLD_BASE, SZ_256K, 0xff000000, 1, AC_RW | SA_IG)
 
 	/*
 	 * TLB entries for SDRAM are not needed on this platform.
@@ -63,12 +64,12 @@ tlbtab:
 	 */
 
 	/* internal ram (l2 cache) */
-	tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_I)
+	tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX | SA_I)
 
 	/* peripherals at f0000000 */
-	tlbentry(CFG_PERIPHERAL_BASE, SZ_4K, CFG_PERIPHERAL_BASE, 1, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, CONFIG_SYS_PERIPHERAL_BASE, 1, AC_RW | SA_IG)
 
 	/* PCI */
-	tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 9, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 9, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 9, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 9, AC_RW | SA_IG)
 	tlbtab_end