X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=board%2Famcc%2Fbamboo%2Fbamboo.c;h=2ffd720d5c4f80d29b56f6e0ceed816435c6ac96;hb=297a65873d2cb2bd296253af51f59cc1391afbff;hp=50771879e1b21ce762cb250565125375f37eaef4;hpb=10a3367955bc2033b288915f8f10d0e507fe2fa1;p=platform%2Fkernel%2Fu-boot.git diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c index 5077187..2ffd720 100644 --- a/board/amcc/bamboo/bamboo.c +++ b/board/amcc/bamboo/bamboo.c @@ -453,7 +453,7 @@ int checkboard(void) } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { #if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)) long dram_size; @@ -462,77 +462,10 @@ long int initdram (int board_type) return dram_size; #else - return CFG_MBYTES_SDRAM << 20; + return CONFIG_SYS_MBYTES_SDRAM << 20; #endif } -#if defined(CFG_DRAM_TEST) -int testdram(void) -{ - unsigned long *mem = (unsigned long *)0; - const unsigned long kend = (1024 / sizeof(unsigned long)); - unsigned long k, n, *p32, ctr; - const unsigned long bend = CFG_MBYTES_SDRAM * 1024 * 1024; - - mtmsr(0); - - for (k = 0; k < CFG_MBYTES_SDRAM*1024; - ++k, mem += (1024 / sizeof(unsigned long))) { - if ((k & 1023) == 0) { - printf("%3d MB\r", k / 1024); - } - - memset(mem, 0xaaaaaaaa, 1024); - for (n = 0; n < kend; ++n) { - if (mem[n] != 0xaaaaaaaa) { - printf("SDRAM test fails at: %08x\n", - (uint) & mem[n]); - return 1; - } - } - - memset(mem, 0x55555555, 1024); - for (n = 0; n < kend; ++n) { - if (mem[n] != 0x55555555) { - printf("SDRAM test fails at: %08x\n", - (uint) & mem[n]); - return 1; - } - } - } - - /* - * Perform a sequence test to ensure that all - * memory locations are uniquely addressable - */ - ctr = 0; - p32 = 0; - while ((unsigned long)p32 != bend) { - if (0 == ((unsigned long)p32 & ((1<<20)-1))) - printf("Writing %3d MB\r", (unsigned long)p32 >> 20); - *p32++ = ctr++; - } - - ctr = 0; - p32 = 0; - while ((unsigned long)p32 != bend) { - if (0 == ((unsigned long)p32 & ((1<<20)-1))) - printf("Verifying %3d MB\r", (unsigned long)p32 >> 20); - - if (*p32 != ctr) { - printf("SDRAM test fails at: %08x\n", p32); - return 1; - } - - ctr++; - p32++; - } - - printf("SDRAM test passes\n"); - return 0; -} -#endif - /************************************************************************* * pci_pre_init * @@ -554,35 +487,35 @@ int pci_pre_init(struct pci_controller *hose) | Set priority for all PLB3 devices to 0. | Set PLB3 arbiter to fair mode. +-------------------------------------------------------------------------*/ - mfsdr(sdr_amp1, addr); - mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(plb3_acr); - mtdcr(plb3_acr, addr | 0x80000000); + mfsdr(SD0_AMP1, addr); + mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(PLB3_ACR); + mtdcr(PLB3_ACR, addr | 0x80000000); /*-------------------------------------------------------------------------+ | Set priority for all PLB4 devices to 0. +-------------------------------------------------------------------------*/ - mfsdr(sdr_amp0, addr); - mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ - mtdcr(plb4_acr, addr); + mfsdr(SD0_AMP0, addr); + mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */ + mtdcr(PLB4_ACR, addr); /*-------------------------------------------------------------------------+ | Set Nebula PLB4 arbiter to fair mode. +-------------------------------------------------------------------------*/ /* Segment0 */ - addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; - addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; - addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; - addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; - mtdcr(plb0_acr, addr); + addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR; + addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED; + addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP; + addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP; + mtdcr(PLB0_ACR, addr); /* Segment1 */ - addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; - addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; - addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; - addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; - mtdcr(plb1_acr, addr); + addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR; + addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED; + addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP; + addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP; + mtdcr(PLB1_ACR, addr); return 1; } @@ -596,7 +529,7 @@ int pci_pre_init(struct pci_controller *hose) * may not be sufficient for a given board. * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) +#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) void pci_target_init(struct pci_controller *hose) { /*--------------------------------------------------------------------------+ @@ -610,14 +543,14 @@ void pci_target_init(struct pci_controller *hose) | Make this region non-prefetchable. +--------------------------------------------------------------------------*/ out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ - out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */ - out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */ + out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ + out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */ out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ - out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */ - out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */ + out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */ + out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */ out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */ @@ -632,8 +565,8 @@ void pci_target_init(struct pci_controller *hose) /* Program the board's subsystem id/vendor id */ pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, - CFG_PCI_SUBSYS_VENDORID); - pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID); + CONFIG_SYS_PCI_SUBSYS_VENDORID); + pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID); /* Configure command register as bus master */ pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); @@ -647,13 +580,13 @@ void pci_target_init(struct pci_controller *hose) pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ +#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ /************************************************************************* * pci_master_init * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) +#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) void pci_master_init(struct pci_controller *hose) { unsigned short temp_short; @@ -668,7 +601,7 @@ void pci_master_init(struct pci_controller *hose) temp_short | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */ +#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */ /************************************************************************* * is_pci_host @@ -762,8 +695,8 @@ void ext_bus_cntlr_init(void) | +-------------------------------------------------------------------------*/ /* NVRAM - FPGA */ - mtebc(pb5ap, EBC0_BNAP_NVRAM_FPGA); - mtebc(pb5cr, EBC0_BNCR_NVRAM_FPGA_CS5); + mtebc(PB5AP, EBC0_BNAP_NVRAM_FPGA); + mtebc(PB5CR, EBC0_BNCR_NVRAM_FPGA_CS5); /*-------------------------------------------------------------------------+ | @@ -816,7 +749,7 @@ void ext_bus_cntlr_init(void) case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN: /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */ /* Read Serial Device Strap Register1 in PPC440EP */ - mfsdr(sdr_sdstp1, sdr0_sdstp1); + mfsdr(SDR0_SDSTP1, sdr0_sdstp1); boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK; ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK; @@ -889,7 +822,7 @@ void ext_bus_cntlr_init(void) /* Default Strap Settings 5-7 */ /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */ /* Read Serial Device Strap Register1 in PPC440EP */ - mfsdr(sdr_sdstp1, sdr0_sdstp1); + mfsdr(SDR0_SDSTP1, sdr0_sdstp1); boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK; ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK; @@ -1080,8 +1013,8 @@ void ext_bus_cntlr_init(void) /*-------------------------------------------------------------------------+ | Initialize EBC CONFIG +-------------------------------------------------------------------------*/ - mtdcr(ebccfga, xbcfg); - mtdcr(ebccfgd, EBC0_CFG_EBTC_DRIVEN | + mtdcr(EBC0_CFGADDR, EBC0_CFG); + mtdcr(EBC0_CFGDATA, EBC0_CFG_EBTC_DRIVEN | EBC0_CFG_PTD_ENABLED | EBC0_CFG_RTC_2048PERCLK | EBC0_CFG_EMPL_LOW | @@ -1096,20 +1029,20 @@ void ext_bus_cntlr_init(void) | Initialize EBC Bank 0-4 +-------------------------------------------------------------------------*/ /* EBC Bank0 */ - mtebc(pb0ap, ebc0_cs0_bnap_value); - mtebc(pb0cr, ebc0_cs0_bncr_value); + mtebc(PB0AP, ebc0_cs0_bnap_value); + mtebc(PB0CR, ebc0_cs0_bncr_value); /* EBC Bank1 */ - mtebc(pb1ap, ebc0_cs1_bnap_value); - mtebc(pb1cr, ebc0_cs1_bncr_value); + mtebc(PB1AP, ebc0_cs1_bnap_value); + mtebc(PB1CR, ebc0_cs1_bncr_value); /* EBC Bank2 */ - mtebc(pb2ap, ebc0_cs2_bnap_value); - mtebc(pb2cr, ebc0_cs2_bncr_value); + mtebc(PB2AP, ebc0_cs2_bnap_value); + mtebc(PB2CR, ebc0_cs2_bncr_value); /* EBC Bank3 */ - mtebc(pb3ap, ebc0_cs3_bnap_value); - mtebc(pb3cr, ebc0_cs3_bncr_value); + mtebc(PB3AP, ebc0_cs3_bnap_value); + mtebc(PB3CR, ebc0_cs3_bncr_value); /* EBC Bank4 */ - mtebc(pb4ap, ebc0_cs4_bnap_value); - mtebc(pb4cr, ebc0_cs4_bncr_value); + mtebc(PB4AP, ebc0_cs4_bnap_value); + mtebc(PB4CR, ebc0_cs4_bncr_value); return; } @@ -2006,10 +1939,10 @@ void configure_ppc440ep_pins(void) sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_USB2D_SEL; sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_DISABLE; - mfsdr(sdr_usb0, sdr0_usb0); + mfsdr(SDR0_USB0, sdr0_usb0); sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK; sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB20D_DEVSEL; - mtsdr(sdr_usb0, sdr0_usb0); + mtsdr(SDR0_USB0, sdr0_usb0); usb2_device_selection_in_fpga(); } @@ -2017,19 +1950,19 @@ void configure_ppc440ep_pins(void) /* USB1.1 Device Selection */ if (ppc440ep_core_selection[USB1_DEVICE] == CORE_SELECTED) { - mfsdr(sdr_usb0, sdr0_usb0); + mfsdr(SDR0_USB0, sdr0_usb0); sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK; sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB11D_DEVSEL; - mtsdr(sdr_usb0, sdr0_usb0); + mtsdr(SDR0_USB0, sdr0_usb0); } /* USB1.1 Host Selection */ if (ppc440ep_core_selection[USB1_HOST] == CORE_SELECTED) { - mfsdr(sdr_usb0, sdr0_usb0); + mfsdr(SDR0_USB0, sdr0_usb0); sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_LEEN_MASK; sdr0_usb0 = sdr0_usb0 | SDR0_USB0_LEEN_ENABLE; - mtsdr(sdr_usb0, sdr0_usb0); + mtsdr(SDR0_USB0, sdr0_usb0); } /* NAND Flash Selection */ @@ -2038,14 +1971,14 @@ void configure_ppc440ep_pins(void) update_ndfc_ios(gpio_tab); #if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)) - mtsdr(sdr_cust0, SDR0_CUST0_MUX_NDFC_SEL | + mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_NDFC_SEL | SDR0_CUST0_NDFC_ENABLE | SDR0_CUST0_NDFC_BW_8_BIT | SDR0_CUST0_NDFC_ARE_MASK | SDR0_CUST0_CHIPSELGAT_EN1 | SDR0_CUST0_CHIPSELGAT_EN2); #else - mtsdr(sdr_cust0, SDR0_CUST0_MUX_NDFC_SEL | + mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_NDFC_SEL | SDR0_CUST0_NDFC_ENABLE | SDR0_CUST0_NDFC_BW_8_BIT | SDR0_CUST0_NDFC_ARE_MASK | @@ -2058,16 +1991,16 @@ void configure_ppc440ep_pins(void) else { /* Set Mux on EMAC */ - mtsdr(sdr_cust0, SDR0_CUST0_MUX_EMAC_SEL); + mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_EMAC_SEL); } /* MII Selection */ if (ppc440ep_core_selection[MII_SEL] == CORE_SELECTED) { update_zii_ios(gpio_tab); - mfsdr(sdr_mfr, sdr0_mfr); + mfsdr(SDR0_MFR, sdr0_mfr); sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_MII; - mtsdr(sdr_mfr, sdr0_mfr); + mtsdr(SDR0_MFR, sdr0_mfr); set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_MII); } @@ -2076,9 +2009,9 @@ void configure_ppc440ep_pins(void) if (ppc440ep_core_selection[RMII_SEL] == CORE_SELECTED) { update_zii_ios(gpio_tab); - mfsdr(sdr_mfr, sdr0_mfr); + mfsdr(SDR0_MFR, sdr0_mfr); sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M; - mtsdr(sdr_mfr, sdr0_mfr); + mtsdr(SDR0_MFR, sdr0_mfr); set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_RMII); } @@ -2087,9 +2020,9 @@ void configure_ppc440ep_pins(void) if (ppc440ep_core_selection[SMII_SEL] == CORE_SELECTED) { update_zii_ios(gpio_tab); - mfsdr(sdr_mfr, sdr0_mfr); + mfsdr(SDR0_MFR, sdr0_mfr); sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_SMII; - mtsdr(sdr_mfr, sdr0_mfr); + mtsdr(SDR0_MFR, sdr0_mfr); set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_SMII); } @@ -2138,13 +2071,13 @@ void configure_ppc440ep_pins(void) /* Packet Reject Function Enable */ if (ppc440ep_core_selection[PACKET_REJ_FUNC_EN] == CORE_SELECTED) { - mfsdr(sdr_mfr, sdr0_mfr); + mfsdr(SDR0_MFR, sdr0_mfr); sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_PKT_REJ_MASK) | SDR0_MFR_PKT_REJ_EN;; - mtsdr(sdr_mfr, sdr0_mfr); + mtsdr(SDR0_MFR, sdr0_mfr); } /* Perform effective access to hardware */ - mtsdr(sdr_pfc1, sdr0_pfc1); + mtsdr(SDR0_PFC1, sdr0_pfc1); set_chip_gpio_configuration(GPIO0, gpio_tab); set_chip_gpio_configuration(GPIO1, gpio_tab);