X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=board%2Famcc%2Facadia%2Facadia.c;h=0db619952eb4c3d39369d70765177a12d76b2da1;hb=297a65873d2cb2bd296253af51f59cc1391afbff;hp=c8aaad2d785ee72f37ce30a2d79783079750a688;hpb=f2b07ebd32e42a5b1126c98efc768ddb8908de62;p=platform%2Fkernel%2Fu-boot.git

diff --git a/board/amcc/acadia/acadia.c b/board/amcc/acadia/acadia.c
index c8aaad2..0db6199 100644
--- a/board/amcc/acadia/acadia.c
+++ b/board/amcc/acadia/acadia.c
@@ -26,94 +26,57 @@
 
 extern void board_pll_init_f(void);
 
-/* Some specific Acadia Defines */
-#define CPLD_BASE	0x80000000
-
-void liveoak_gpio_init(void)
+static void acadia_gpio_init(void)
 {
 	/*
 	 * GPIO0 setup (select GPIO or alternate function)
 	 */
-       	out32(GPIO0_OSRL, CFG_GPIO0_OSRL);
-       	out32(GPIO0_OSRH, CFG_GPIO0_OSRH);	/* output select */
-       	out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L);
-       	out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H);	/* input select */
-       	out32(GPIO0_TSRL, CFG_GPIO0_TSRL);
-       	out32(GPIO0_TSRH, CFG_GPIO0_TSRH);	/* three-state select */
-       	out32(GPIO0_TCR, CFG_GPIO0_TCR);  /* enable output driver for outputs */
+	out32(GPIO0_OSRL, CONFIG_SYS_GPIO0_OSRL);
+	out32(GPIO0_OSRH, CONFIG_SYS_GPIO0_OSRH);	/* output select */
+	out32(GPIO0_ISR1L, CONFIG_SYS_GPIO0_ISR1L);
+	out32(GPIO0_ISR1H, CONFIG_SYS_GPIO0_ISR1H);	/* input select */
+	out32(GPIO0_TSRL, CONFIG_SYS_GPIO0_TSRL);
+	out32(GPIO0_TSRH, CONFIG_SYS_GPIO0_TSRH);	/* three-state select */
+	out32(GPIO0_TCR, CONFIG_SYS_GPIO0_TCR);  /* enable output driver for outputs */
 
 	/*
 	 * Ultra (405EZ) was nice enough to add another GPIO controller
 	 */
-	out32(GPIO1_OSRH, CFG_GPIO1_OSRH);	/* output select */
-	out32(GPIO1_OSRL, CFG_GPIO1_OSRL);
-	out32(GPIO1_ISR1H, CFG_GPIO1_ISR1H);	/* input select */
-	out32(GPIO1_ISR1L, CFG_GPIO1_ISR1L);
-	out32(GPIO1_TSRH, CFG_GPIO1_TSRH);	/* three-state select */
-	out32(GPIO1_TSRL, CFG_GPIO1_TSRL);
-	out32(GPIO1_TCR, CFG_GPIO1_TCR);  /* enable output driver for outputs */
+	out32(GPIO1_OSRH, CONFIG_SYS_GPIO1_OSRH);	/* output select */
+	out32(GPIO1_OSRL, CONFIG_SYS_GPIO1_OSRL);
+	out32(GPIO1_ISR1H, CONFIG_SYS_GPIO1_ISR1H);	/* input select */
+	out32(GPIO1_ISR1L, CONFIG_SYS_GPIO1_ISR1L);
+	out32(GPIO1_TSRH, CONFIG_SYS_GPIO1_TSRH);	/* three-state select */
+	out32(GPIO1_TSRL, CONFIG_SYS_GPIO1_TSRL);
+	out32(GPIO1_TCR, CONFIG_SYS_GPIO1_TCR);  /* enable output driver for outputs */
 }
 
-#if 0 /* test-only: not called at all??? */
-void ext_bus_cntlr_init(void)
-{
-#if (defined(EBC_PB4AP) && defined(EBC_PB4CR) && !(CFG_INIT_DCACHE_CS == 4))
-       	mtebc(pb4ap, EBC_PB4AP);
-       	mtebc(pb4cr, EBC_PB4CR);
-#endif
-}
-#endif
-
 int board_early_init_f(void)
 {
 	unsigned int reg;
 
-#if 0 /* test-only */
-	/*
-	 * If CRAM memory and SPI/NAND boot, and if the CRAM memory is
-	 * already initialized by the pre-loader then we can't reinitialize
-	 * CPR registers, GPIO registers and EBC registers as this will
-	 * have the effect of un-initializing CRAM.
-	 */
-	spr_reg = (volatile unsigned long) mfspr(SPRG7);
-	if (spr_reg != LOAK_CRAM) { /* != CRAM */
+#if !defined(CONFIG_NAND_U_BOOT)
+	/* don't reinit PLL when booting via I2C bootstrap option */
+	mfsdr(SDR0_PINSTP, reg);
+	if (reg != 0xf0000000)
 		board_pll_init_f();
-		liveoak_gpio_init();
-		ext_bus_cntlr_init();
-
-		mtebc(pb1ap, CFG_EBC_PB1AP);
-		mtebc(pb1cr, CFG_EBC_PB1CR);
-
-		mtebc(pb2ap, CFG_EBC_PB2AP);
-		mtebc(pb2cr, CFG_EBC_PB2CR);
-	}
-#else
-	board_pll_init_f();
-	liveoak_gpio_init();
-/*	ext_bus_cntlr_init(); */
 #endif
 
-#if 0 /* test-only (orig) */
-	/*
-	 * If we boot from NAND Flash, we are running in
-	 * RAM, so disable the EBC_CS0 so that it goes back
-	 * to the NOR Flash.  It will be enabled later
-	 * for the NAND Flash on EBC_CS1
-	 */
-	mfsdr(sdrultra0, reg);
-	mtsdr(sdrultra0, reg & ~SDR_ULTRA0_CSNSEL0);
-#endif
-#if 0 /* test-only */
-	/* configure for NAND */
-	mfsdr(sdrultra0, reg);
+	acadia_gpio_init();
+
+	/* Configure 405EZ for NAND usage */
+	mtsdr(SDR0_NAND0, SDR_NAND0_NDEN | SDR_NAND0_NDAREN | SDR_NAND0_NDRBEN);
+	mfsdr(SDR0_ULTRA0, reg);
 	reg &= ~SDR_ULTRA0_CSN_MASK;
-	reg |= SDR_ULTRA0_CSNSEL0 >> CFG_NAND_CS;
-	mtsdr(sdrultra0, reg & ~SDR_ULTRA0_CSNSEL0);
-#endif
+	reg |= (SDR_ULTRA0_CSNSEL0 >> CONFIG_SYS_NAND_CS) |
+		SDR_ULTRA0_NDGPIOBP |
+		SDR_ULTRA0_EBCRDYEN |
+		SDR_ULTRA0_NFSRSTEN;
+	mtsdr(SDR0_ULTRA0, reg);
 
 	/* USB Host core needs this bit set */
-	mfsdr(sdrultra1, reg);
-	mtsdr(sdrultra1, reg | SDR_ULTRA1_LEDNENABLE);
+	mfsdr(SDR0_ULTRA1, reg);
+	mtsdr(SDR0_ULTRA1, reg | SDR_ULTRA1_LEDNENABLE);
 
 	mtdcr(uicsr, 0xFFFFFFFF);	/* clear all ints */
 	mtdcr(uicer, 0x00000000);	/* disable all ints */
@@ -128,7 +91,7 @@ int board_early_init_f(void)
 int misc_init_f(void)
 {
 	/* Set EPLD to take PHY out of reset */
-	out8(CPLD_BASE + 0x05, 0x00);
+	out8(CONFIG_SYS_CPLD_BASE + 0x05, 0x00);
 	udelay(100000);
 
 	return 0;
@@ -140,8 +103,11 @@ int misc_init_f(void)
 int checkboard(void)
 {
 	char *s = getenv("serial#");
+	u8 rev;
+
+	rev = in8(CONFIG_SYS_CPLD_BASE + 0);
+	printf("Board: Acadia - AMCC PPC405EZ Evaluation Board, Rev. %X", rev);
 
-	printf("Board: Acadia - AMCC PPC405EZ Evaluation Board");
 	if (s != NULL) {
 		puts(", serial# ");
 		puts(s);