X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=arch%2Fx86%2Fdts%2Fconga-qeval20-qa3-e3845.dts;h=c6577b30c8da1153dff696aa2174df4c8a73df51;hb=605bc145f91d2a28ba2e517cae4e53e255e34b6f;hp=5884dbc277d36e0507105d287e8d8d7dfaac4a05;hpb=83853366e3f9eb76426a6b1bda810e470bce04f0;p=platform%2Fkernel%2Fu-boot.git

diff --git a/arch/x86/dts/conga-qeval20-qa3-e3845.dts b/arch/x86/dts/conga-qeval20-qa3-e3845.dts
index 5884dbc..c6577b3 100644
--- a/arch/x86/dts/conga-qeval20-qa3-e3845.dts
+++ b/arch/x86/dts/conga-qeval20-qa3-e3845.dts
@@ -14,7 +14,9 @@
 /include/ "serial.dtsi"
 /include/ "reset.dtsi"
 /include/ "rtc.dtsi"
-/include/ "tsc_timer.dtsi"
+
+#include "tsc_timer.dtsi"
+#include "smbios.dtsi"
 
 / {
 	model = "congatec-QEVAL20-QA3-E3845";
@@ -101,7 +103,7 @@
 		compatible = "intel,pci-baytrail", "pci-x86";
 		#address-cells = <3>;
 		#size-cells = <2>;
-		u-boot,dm-pre-reloc;
+		bootph-all;
 		ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
 			  0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
 			  0x01000000 0x0 0x2000 0x2000 0 0xe000>;
@@ -185,19 +187,20 @@
 					#address-cells = <1>;
 					#size-cells = <1>;
 					reg = <0>;
+					m25p,fast-read;
 					compatible = "stmicro,n25q064a",
-						"spi-flash";
+						"jedec,spi-nor";
 					memory-map = <0xff800000 0x00800000>;
 					rw-mrc-cache {
 						label = "rw-mrc-cache";
-						reg = <0x006f0000 0x00010000>;
+						reg = <0x005f0000 0x00010000>;
 					};
 				};
 			};
 
 			gpioa {
 				compatible = "intel,ich6-gpio";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				reg = <0 0x20>;
 				bank-name = "A";
 				use-lvl-write-cache;
@@ -205,7 +208,7 @@
 
 			gpiob {
 				compatible = "intel,ich6-gpio";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				reg = <0x20 0x20>;
 				bank-name = "B";
 				use-lvl-write-cache;
@@ -213,7 +216,7 @@
 
 			gpioc {
 				compatible = "intel,ich6-gpio";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				reg = <0x40 0x20>;
 				bank-name = "C";
 				use-lvl-write-cache;
@@ -221,7 +224,7 @@
 
 			gpiod {
 				compatible = "intel,ich6-gpio";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				reg = <0x60 0x20>;
 				bank-name = "D";
 				use-lvl-write-cache;
@@ -229,7 +232,7 @@
 
 			gpioe {
 				compatible = "intel,ich6-gpio";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				reg = <0x80 0x20>;
 				bank-name = "E";
 				use-lvl-write-cache;
@@ -237,7 +240,7 @@
 
 			gpiof {
 				compatible = "intel,ich6-gpio";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				reg = <0xA0 0x20>;
 				bank-name = "F";
 				use-lvl-write-cache;