X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=arch%2Fx86%2Fdts%2Fbaytrail_som-db5800-som-6867.dts;h=4e12c4a40cb16cfa2ebf963e25990ea3a35cd1ed;hb=605bc145f91d2a28ba2e517cae4e53e255e34b6f;hp=aa8bfb86513c4fa9571a548058616e911b445c45;hpb=770ee0174223e824a721f5f164cc8b2bf7473189;p=platform%2Fkernel%2Fu-boot.git

diff --git a/arch/x86/dts/baytrail_som-db5800-som-6867.dts b/arch/x86/dts/baytrail_som-db5800-som-6867.dts
index aa8bfb8..4e12c4a 100644
--- a/arch/x86/dts/baytrail_som-db5800-som-6867.dts
+++ b/arch/x86/dts/baytrail_som-db5800-som-6867.dts
@@ -1,19 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
  * Copyright (C) 2016, George McCollister <george.mccollister@gmail.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
  */
 
 /dts-v1/;
 
+#include <asm/arch-baytrail/fsp/fsp_configs.h>
 #include <dt-bindings/gpio/x86-gpio.h>
 #include <dt-bindings/interrupt-router/intel-irq.h>
 
 /include/ "skeleton.dtsi"
 /include/ "serial.dtsi"
+/include/ "reset.dtsi"
 /include/ "rtc.dtsi"
-/include/ "tsc_timer.dtsi"
+
+#include "tsc_timer.dtsi"
+#include "smbios.dtsi"
 
 / {
 	model = "Advantech SOM-DB5800-SOM-6867";
@@ -113,7 +116,7 @@
 		compatible = "intel,pci-baytrail", "pci-x86";
 		#address-cells = <3>;
 		#size-cells = <2>;
-		u-boot,dm-pre-reloc;
+		bootph-all;
 		ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
 			  0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
 			  0x01000000 0x0 0x2000 0x2000 0 0xe000>;
@@ -197,19 +200,20 @@
 					#address-cells = <1>;
 					#size-cells = <1>;
 					reg = <0>;
+					m25p,fast-read;
 					compatible = "macronix,mx25l6405d",
-						"spi-flash";
+						"jedec,spi-nor";
 					memory-map = <0xff800000 0x00800000>;
 					rw-mrc-cache {
 						label = "rw-mrc-cache";
-						reg = <0x006f0000 0x00010000>;
+						reg = <0x005f0000 0x00010000>;
 					};
 				};
 			};
 
 			gpioa {
 				compatible = "intel,ich6-gpio";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				reg = <0 0x20>;
 				bank-name = "A";
 				use-lvl-write-cache;
@@ -217,7 +221,7 @@
 
 			gpiob {
 				compatible = "intel,ich6-gpio";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				reg = <0x20 0x20>;
 				bank-name = "B";
 				use-lvl-write-cache;
@@ -225,7 +229,7 @@
 
 			gpioc {
 				compatible = "intel,ich6-gpio";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				reg = <0x40 0x20>;
 				bank-name = "C";
 				use-lvl-write-cache;
@@ -233,7 +237,7 @@
 
 			gpiod {
 				compatible = "intel,ich6-gpio";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				reg = <0x60 0x20>;
 				bank-name = "D";
 				use-lvl-write-cache;
@@ -241,7 +245,7 @@
 
 			gpioe {
 				compatible = "intel,ich6-gpio";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				reg = <0x80 0x20>;
 				bank-name = "E";
 				use-lvl-write-cache;
@@ -249,7 +253,7 @@
 
 			gpiof {
 				compatible = "intel,ich6-gpio";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				reg = <0xA0 0x20>;
 				bank-name = "F";
 				use-lvl-write-cache;
@@ -259,15 +263,15 @@
 
 	fsp {
 		compatible = "intel,baytrail-fsp";
-		fsp,mrc-init-tseg-size = <0>;
-		fsp,mrc-init-mmio-size = <0x800>;
+		fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_1MB>;
+		fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>;
 		fsp,mrc-init-spd-addr1 = <0xa0>;
 		fsp,mrc-init-spd-addr2 = <0xa2>;
 		fsp,enable-spi;
 		fsp,enable-sata;
-		fsp,sata-mode = <1>;
+		fsp,sata-mode = <SATA_MODE_AHCI>;
 		fsp,enable-azalia;
-		fsp,lpss-sio-enable-pci-mode;
+		fsp,lpss-sio-mode = <LPSS_SIO_MODE_PCI>;
 		fsp,enable-dma0;
 		fsp,enable-dma1;
 		fsp,enable-i2c0;
@@ -279,14 +283,12 @@
 		fsp,enable-i2c6;
 		fsp,enable-pwm0;
 		fsp,enable-pwm1;
-		fsp,igd-dvmt50-pre-alloc = <2>;
-		fsp,aperture-size = <2>;
-		fsp,gtt-size = <2>;
-		fsp,scc-enable-pci-mode;
-		fsp,os-selection = <4>;
+		fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_64MB>;
+		fsp,aperture-size = <APERTURE_SIZE_256MB>;
+		fsp,gtt-size = <GTT_SIZE_2MB>;
+		fsp,scc-mode = <SCC_MODE_PCI>;
+		fsp,os-selection = <OS_SELECTION_LINUX>;
 		fsp,enable-igd;
-		fsp,serial-debug-port-address = <0x3f8>;
-		fsp,serial-debug-port-type = <1>;
 	};
 
 	microcode {