X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=arch%2Fx86%2Fdts%2Fbayleybay.dts;h=59403f40cee6a14ac1c67ffeea92417366ab89e6;hb=605bc145f91d2a28ba2e517cae4e53e255e34b6f;hp=cdd51215c1d2be68e7de5e62cebb9c984b90b00d;hpb=1f9eb59d273983ba8c65368120285ac6425476f7;p=platform%2Fkernel%2Fu-boot.git

diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts
index cdd5121..59403f4 100644
--- a/arch/x86/dts/bayleybay.dts
+++ b/arch/x86/dts/bayleybay.dts
@@ -1,19 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
  */
 
 /dts-v1/;
 
+#include <asm/arch-baytrail/fsp/fsp_configs.h>
 #include <dt-bindings/gpio/x86-gpio.h>
 #include <dt-bindings/interrupt-router/intel-irq.h>
 
 /include/ "skeleton.dtsi"
 /include/ "keyboard.dtsi"
 /include/ "serial.dtsi"
+/include/ "reset.dtsi"
 /include/ "rtc.dtsi"
-/include/ "tsc_timer.dtsi"
+
+#include "tsc_timer.dtsi"
+#include "smbios.dtsi"
 
 / {
 	model = "Intel Bayley Bay";
@@ -65,53 +68,31 @@
 		};
 	};
 
-	gpioa {
-		compatible = "intel,ich6-gpio";
-		u-boot,dm-pre-reloc;
-		reg = <0 0x20>;
-		bank-name = "A";
-	};
-
-	gpiob {
-		compatible = "intel,ich6-gpio";
-		u-boot,dm-pre-reloc;
-		reg = <0x20 0x20>;
-		bank-name = "B";
-	};
-
-	gpioc {
-		compatible = "intel,ich6-gpio";
-		u-boot,dm-pre-reloc;
-		reg = <0x40 0x20>;
-		bank-name = "C";
-	};
-
-	gpiod {
-		compatible = "intel,ich6-gpio";
-		u-boot,dm-pre-reloc;
-		reg = <0x60 0x20>;
-		bank-name = "D";
-	};
-
-	gpioe {
-		compatible = "intel,ich6-gpio";
-		u-boot,dm-pre-reloc;
-		reg = <0x80 0x20>;
-		bank-name = "E";
-	};
+	pch_pinctrl {
+		compatible = "intel,x86-pinctrl";
+		reg = <0 0>;
 
-	gpiof {
-		compatible = "intel,ich6-gpio";
-		u-boot,dm-pre-reloc;
-		reg = <0xA0 0x20>;
-		bank-name = "F";
+		/*
+		 * As of today, the latest version FSP (gold4) for BayTrail
+		 * misses the PAD configuration of the SD controller's Card
+		 * Detect signal. The default PAD value for the CD pin sets
+		 * the pin to work in GPIO mode, which causes card detect
+		 * status cannot be reflected by the Present State register
+		 * in the SD controller (bit 16 & bit 18 are always zero).
+		 *
+		 * Configure this pin to function 1 (SD controller).
+		 */
+		sdmmc3_cd@0 {
+			pad-offset = <0x3a0>;
+			mode-func = <1>;
+		};
 	};
 
 	pci {
 		compatible = "pci-x86";
 		#address-cells = <3>;
 		#size-cells = <2>;
-		u-boot,dm-pre-reloc;
+		bootph-all;
 		ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
 			  0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
 			  0x01000000 0x0 0x2000 0x2000 0 0xe000>;
@@ -119,11 +100,14 @@
 		pch@1f,0 {
 			reg = <0x0000f800 0 0 0 0>;
 			compatible = "intel,pch9";
+			#address-cells = <1>;
+			#size-cells = <1>;
 
 			irq-router {
 				compatible = "intel,irq-router";
 				intel,pirq-config = "ibase";
 				intel,ibase-offset = <0x50>;
+				intel,actl-addr = <0>;
 				intel,pirq-link = <8 8>;
 				intel,pirq-mask = <0xdee0>;
 				intel,pirq-routing = <
@@ -192,33 +176,82 @@
 					#address-cells = <1>;
 					#size-cells = <1>;
 					reg = <0>;
+					m25p,fast-read;
 					compatible = "winbond,w25q64dw",
-						"spi-flash";
+						"jedec,spi-nor";
 					memory-map = <0xff800000 0x00800000>;
 					rw-mrc-cache {
 						label = "rw-mrc-cache";
-						reg = <0x006e0000 0x00010000>;
+						reg = <0x005e0000 0x00010000>;
 					};
 				};
 			};
+
+			gpioa {
+				compatible = "intel,ich6-gpio";
+				bootph-all;
+				reg = <0 0x20>;
+				bank-name = "A";
+				use-lvl-write-cache;
+			};
+
+			gpiob {
+				compatible = "intel,ich6-gpio";
+				bootph-all;
+				reg = <0x20 0x20>;
+				bank-name = "B";
+				use-lvl-write-cache;
+			};
+
+			gpioc {
+				compatible = "intel,ich6-gpio";
+				bootph-all;
+				reg = <0x40 0x20>;
+				bank-name = "C";
+				use-lvl-write-cache;
+			};
+
+			gpiod {
+				compatible = "intel,ich6-gpio";
+				bootph-all;
+				reg = <0x60 0x20>;
+				bank-name = "D";
+				use-lvl-write-cache;
+			};
+
+			gpioe {
+				compatible = "intel,ich6-gpio";
+				bootph-all;
+				reg = <0x80 0x20>;
+				bank-name = "E";
+				use-lvl-write-cache;
+			};
+
+			gpiof {
+				compatible = "intel,ich6-gpio";
+				bootph-all;
+				reg = <0xA0 0x20>;
+				bank-name = "F";
+				use-lvl-write-cache;
+			};
 		};
 	};
 
 	fsp {
 		compatible = "intel,baytrail-fsp";
-		fsp,mrc-init-tseg-size = <0>;
-		fsp,mrc-init-mmio-size = <0x800>;
+		fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_1MB>;
+		fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>;
 		fsp,mrc-init-spd-addr1 = <0xa0>;
 		fsp,mrc-init-spd-addr2 = <0xa2>;
-		fsp,emmc-boot-mode = <2>;
+		fsp,emmc-boot-mode = <EMMC_BOOT_MODE_AUTO>;
 		fsp,enable-sdio;
 		fsp,enable-sdcard;
 		fsp,enable-hsuart1;
 		fsp,enable-spi;
 		fsp,enable-sata;
-		fsp,sata-mode = <1>;
-		fsp,enable-lpe;
-		fsp,lpss-sio-enable-pci-mode;
+		fsp,sata-mode = <SATA_MODE_AHCI>;
+		fsp,lpe-mode = <LPE_MODE_PCI>;
+		fsp,lpss-sio-mode = <LPSS_SIO_MODE_PCI>;
 		fsp,enable-dma0;
 		fsp,enable-dma1;
 		fsp,enable-i2c0;
@@ -230,13 +263,11 @@
 		fsp,enable-i2c6;
 		fsp,enable-pwm0;
 		fsp,enable-pwm1;
-		fsp,igd-dvmt50-pre-alloc = <2>;
-		fsp,aperture-size = <2>;
-		fsp,gtt-size = <2>;
-		fsp,serial-debug-port-address = <0x3f8>;
-		fsp,serial-debug-port-type = <1>;
-		fsp,scc-enable-pci-mode;
-		fsp,os-selection = <4>;
+		fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_64MB>;
+		fsp,aperture-size = <APERTURE_SIZE_256MB>;
+		fsp,gtt-size = <GTT_SIZE_2MB>;
+		fsp,scc-mode = <SCC_MODE_PCI>;
+		fsp,os-selection = <OS_SELECTION_LINUX>;
 		fsp,emmc45-ddr50-enabled;
 		fsp,emmc45-retune-timer-value = <8>;
 		fsp,enable-igd;
@@ -247,10 +278,10 @@
 #include "microcode/m0230671117.dtsi"
 		};
 		update@1 {
-#include "microcode/m0130673322.dtsi"
+#include "microcode/m0130673325.dtsi"
 		};
 		update@2 {
-#include "microcode/m0130679901.dtsi"
+#include "microcode/m0130679907.dtsi"
 		};
 	};