X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=arch%2Fx86%2Fdts%2Fbayleybay.dts;h=59403f40cee6a14ac1c67ffeea92417366ab89e6;hb=605bc145f91d2a28ba2e517cae4e53e255e34b6f;hp=c8907ce44bcdcf7296db77ac7eb021441bf8997d;hpb=b57129dbdade13ee152daf15a4221d8582f48387;p=platform%2Fkernel%2Fu-boot.git diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts index c8907ce..59403f4 100644 --- a/arch/x86/dts/bayleybay.dts +++ b/arch/x86/dts/bayleybay.dts @@ -1,19 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2015, Bin Meng - * - * SPDX-License-Identifier: GPL-2.0+ */ /dts-v1/; +#include #include #include /include/ "skeleton.dtsi" /include/ "keyboard.dtsi" /include/ "serial.dtsi" +/include/ "reset.dtsi" /include/ "rtc.dtsi" -/include/ "tsc_timer.dtsi" + +#include "tsc_timer.dtsi" +#include "smbios.dtsi" / { model = "Intel Bayley Bay"; @@ -89,7 +92,7 @@ compatible = "pci-x86"; #address-cells = <3>; #size-cells = <2>; - u-boot,dm-pre-reloc; + bootph-all; ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000 0x01000000 0x0 0x2000 0x2000 0 0xe000>; @@ -173,75 +176,82 @@ #address-cells = <1>; #size-cells = <1>; reg = <0>; + m25p,fast-read; compatible = "winbond,w25q64dw", - "spi-flash"; + "jedec,spi-nor"; memory-map = <0xff800000 0x00800000>; rw-mrc-cache { label = "rw-mrc-cache"; - reg = <0x006e0000 0x00010000>; + reg = <0x005e0000 0x00010000>; }; }; }; gpioa { compatible = "intel,ich6-gpio"; - u-boot,dm-pre-reloc; + bootph-all; reg = <0 0x20>; bank-name = "A"; + use-lvl-write-cache; }; gpiob { compatible = "intel,ich6-gpio"; - u-boot,dm-pre-reloc; + bootph-all; reg = <0x20 0x20>; bank-name = "B"; + use-lvl-write-cache; }; gpioc { compatible = "intel,ich6-gpio"; - u-boot,dm-pre-reloc; + bootph-all; reg = <0x40 0x20>; bank-name = "C"; + use-lvl-write-cache; }; gpiod { compatible = "intel,ich6-gpio"; - u-boot,dm-pre-reloc; + bootph-all; reg = <0x60 0x20>; bank-name = "D"; + use-lvl-write-cache; }; gpioe { compatible = "intel,ich6-gpio"; - u-boot,dm-pre-reloc; + bootph-all; reg = <0x80 0x20>; bank-name = "E"; + use-lvl-write-cache; }; gpiof { compatible = "intel,ich6-gpio"; - u-boot,dm-pre-reloc; + bootph-all; reg = <0xA0 0x20>; bank-name = "F"; + use-lvl-write-cache; }; }; }; fsp { compatible = "intel,baytrail-fsp"; - fsp,mrc-init-tseg-size = <0>; - fsp,mrc-init-mmio-size = <0x800>; + fsp,mrc-init-tseg-size = ; + fsp,mrc-init-mmio-size = ; fsp,mrc-init-spd-addr1 = <0xa0>; fsp,mrc-init-spd-addr2 = <0xa2>; - fsp,emmc-boot-mode = <1>; + fsp,emmc-boot-mode = ; fsp,enable-sdio; fsp,enable-sdcard; fsp,enable-hsuart1; fsp,enable-spi; fsp,enable-sata; - fsp,sata-mode = <1>; - fsp,enable-lpe; - fsp,lpss-sio-enable-pci-mode; + fsp,sata-mode = ; + fsp,lpe-mode = ; + fsp,lpss-sio-mode = ; fsp,enable-dma0; fsp,enable-dma1; fsp,enable-i2c0; @@ -253,13 +263,11 @@ fsp,enable-i2c6; fsp,enable-pwm0; fsp,enable-pwm1; - fsp,igd-dvmt50-pre-alloc = <2>; - fsp,aperture-size = <2>; - fsp,gtt-size = <2>; - fsp,serial-debug-port-address = <0x3f8>; - fsp,serial-debug-port-type = <1>; - fsp,scc-enable-pci-mode; - fsp,os-selection = <4>; + fsp,igd-dvmt50-pre-alloc = ; + fsp,aperture-size = ; + fsp,gtt-size = ; + fsp,scc-mode = ; + fsp,os-selection = ; fsp,emmc45-ddr50-enabled; fsp,emmc45-retune-timer-value = <8>; fsp,enable-igd;