X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=arch%2Friscv%2FKconfig;h=4b0c3dffa6b1e3a8a57304069e6d1dcfb564c58f;hb=8a44fe69439438797b93b2e7dd70e1a8fad31519;hp=f49618d24d2675e91b21598150bbb40a3ae3160f;hpb=d91cf006ee42c914573faeff3ca5a5a64ea71d8f;p=platform%2Fkernel%2Fu-boot.git diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index f49618d..4b0c3df 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -17,8 +17,17 @@ config TARGET_MICROCHIP_ICICLE config TARGET_QEMU_VIRT bool "Support QEMU Virt Board" -config TARGET_SIFIVE_FU540 - bool "Support SiFive FU540 Board" +config TARGET_SIFIVE_UNLEASHED + bool "Support SiFive Unleashed Board" + +config TARGET_SIFIVE_UNMATCHED + bool "Support SiFive Unmatched Board" + +config TARGET_SIPEED_MAIX + bool "Support Sipeed Maix Board" + +config TARGET_OPENPITON_RISCV64 + bool "Support RISC-V cores on OpenPiton SoC" endchoice @@ -52,10 +61,15 @@ config SPL_SYS_DCACHE_OFF source "board/AndesTech/ax25-ae350/Kconfig" source "board/emulation/qemu-riscv/Kconfig" source "board/microchip/mpfs_icicle/Kconfig" -source "board/sifive/fu540/Kconfig" +source "board/sifive/unleashed/Kconfig" +source "board/sifive/unmatched/Kconfig" +source "board/openpiton/riscv64/Kconfig" +source "board/sipeed/maix/Kconfig" # platform-specific options below source "arch/riscv/cpu/ax25/Kconfig" +source "arch/riscv/cpu/fu540/Kconfig" +source "arch/riscv/cpu/fu740/Kconfig" source "arch/riscv/cpu/generic/Kconfig" # architecture-specific options below @@ -147,29 +161,25 @@ config 32BIT config 64BIT bool +config DMA_ADDR_T_64BIT + bool + default y if 64BIT + config SIFIVE_CLINT bool - depends on RISCV_MMODE || SPL_RISCV_MMODE - select REGMAP - select SYSCON - select SPL_REGMAP if SPL - select SPL_SYSCON if SPL + depends on RISCV_MMODE help The SiFive CLINT block holds memory-mapped control and status registers associated with software and timer interrupts. -config ANDES_PLIC +config SPL_SIFIVE_CLINT bool - depends on RISCV_MMODE || SPL_RISCV_MMODE - select REGMAP - select SYSCON - select SPL_REGMAP if SPL - select SPL_SYSCON if SPL + depends on SPL_RISCV_MMODE help - The Andes PLIC block holds memory-mapped claim and pending registers - associated with software interrupt. + The SiFive CLINT block holds memory-mapped control and status registers + associated with software and timer interrupts. -config ANDES_PLMT +config ANDES_PLIC bool depends on RISCV_MMODE || SPL_RISCV_MMODE select REGMAP @@ -177,22 +187,15 @@ config ANDES_PLMT select SPL_REGMAP if SPL select SPL_SYSCON if SPL help - The Andes PLMT block holds memory-mapped mtime register - associated with timer tick. - -config RISCV_RDTIME - bool - default y if RISCV_SMODE || SPL_RISCV_SMODE - help - The provides the riscv_get_time() API that is implemented using the - standard rdtime instruction. This is the case for S-mode U-Boot, and - is useful for processors that support rdtime in M-mode too. + The Andes PLIC block holds memory-mapped claim and pending registers + associated with software interrupt. config SYS_MALLOC_F_LEN default 0x1000 config SMP bool "Symmetric Multi-Processing" + depends on SBI_V01 || !RISCV_SMODE help This enables support for systems with more than one CPU. If you say N here, U-Boot will run on single and multiprocessor @@ -200,18 +203,60 @@ config SMP machine. If you say Y here, U-Boot will run on many, but not all, single processor machines. +config SPL_SMP + bool "Symmetric Multi-Processing in SPL" + depends on SPL && SPL_RISCV_MMODE + default y + help + This enables support for systems with more than one CPU in SPL. + If you say N here, U-Boot SPL will run on single and multiprocessor + machines, but will use only one CPU of a multiprocessor + machine. If you say Y here, U-Boot SPL will run on many, but not + all, single processor machines. + config NR_CPUS int "Maximum number of CPUs (2-32)" range 2 32 - depends on SMP + depends on SMP || SPL_SMP default 8 help On multiprocessor machines, U-Boot sets up a stack for each CPU. Stack memory is pre-allocated. U-Boot must therefore know the maximum number of CPUs that may be present. +config SBI + bool + default y if RISCV_SMODE || SPL_RISCV_SMODE + +choice + prompt "SBI support" + default SBI_V02 + +config SBI_V01 + bool "SBI v0.1 support" + depends on SBI + help + This config allows kernel to use SBI v0.1 APIs. This will be + deprecated in future once legacy M-mode software are no longer in use. + +config SBI_V02 + bool "SBI v0.2 support" + depends on SBI + help + This config allows kernel to use SBI v0.2 APIs. SBI v0.2 is more + scalable and extendable to handle future needs for RISC-V supervisor + interfaces. For example, with SBI v0.2 HSM extension, only a single + hart need to boot and enter operating system. The booting hart can + bring up secondary harts one by one afterwards. + + Choose this option if OpenSBI v0.7 or above release is used together + with U-Boot. + +endchoice + config SBI_IPI bool + depends on SBI default y if RISCV_SMODE || SPL_RISCV_SMODE depends on SMP @@ -225,8 +270,103 @@ config XIP config SHOW_REGS bool "Show registers on unhandled exception" +config RISCV_PRIV_1_9 + bool "Use version 1.9 of the RISC-V priviledged specification" + help + Older versions of the RISC-V priviledged specification had + separate counter enable CSRs for each privilege mode. Writing + to the unified mcounteren CSR on a processor implementing the + old specification will result in an illegal instruction + exception. In addition to counter CSR changes, the way virtual + memory is configured was also changed. + config STACK_SIZE_SHIFT int default 14 +config OF_BOARD_FIXUP + default y if OF_SEPARATE && RISCV_SMODE + +menu "Use assembly optimized implementation of memory routines" + +config USE_ARCH_MEMCPY + bool "Use an assembly optimized implementation of memcpy" + default y + help + Enable the generation of an optimized version of memcpy. + Such an implementation may be faster under some conditions + but may increase the binary size. + +config SPL_USE_ARCH_MEMCPY + bool "Use an assembly optimized implementation of memcpy for SPL" + default y if USE_ARCH_MEMCPY + depends on SPL + help + Enable the generation of an optimized version of memcpy. + Such an implementation may be faster under some conditions + but may increase the binary size. + +config TPL_USE_ARCH_MEMCPY + bool "Use an assembly optimized implementation of memcpy for TPL" + default y if USE_ARCH_MEMCPY + depends on TPL + help + Enable the generation of an optimized version of memcpy. + Such an implementation may be faster under some conditions + but may increase the binary size. + +config USE_ARCH_MEMMOVE + bool "Use an assembly optimized implementation of memmove" + default y + help + Enable the generation of an optimized version of memmove. + Such an implementation may be faster under some conditions + but may increase the binary size. + +config SPL_USE_ARCH_MEMMOVE + bool "Use an assembly optimized implementation of memmove for SPL" + default y if USE_ARCH_MEMCPY + depends on SPL + help + Enable the generation of an optimized version of memmove. + Such an implementation may be faster under some conditions + but may increase the binary size. + +config TPL_USE_ARCH_MEMMOVE + bool "Use an assembly optimized implementation of memmove for TPL" + default y if USE_ARCH_MEMCPY + depends on TPL + help + Enable the generation of an optimized version of memmove. + Such an implementation may be faster under some conditions + but may increase the binary size. + +config USE_ARCH_MEMSET + bool "Use an assembly optimized implementation of memset" + default y + help + Enable the generation of an optimized version of memset. + Such an implementation may be faster under some conditions + but may increase the binary size. + +config SPL_USE_ARCH_MEMSET + bool "Use an assembly optimized implementation of memset for SPL" + default y if USE_ARCH_MEMSET + depends on SPL + help + Enable the generation of an optimized version of memset. + Such an implementation may be faster under some conditions + but may increase the binary size. + +config TPL_USE_ARCH_MEMSET + bool "Use an assembly optimized implementation of memset for TPL" + default y if USE_ARCH_MEMSET + depends on TPL + help + Enable the generation of an optimized version of memset. + Such an implementation may be faster under some conditions + but may increase the binary size. + +endmenu + endmenu