X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=arch%2Fpowerpc%2Finclude%2Fasm%2Fimmap_85xx.h;h=70112c91fc51e09962bd001e053d4f47bc1885db;hb=ed7fe2bee12a464da5b944cc2218d924793b8a80;hp=8ec2a38aad4d7ed2e971d51aa9d5f738cc4cb3b2;hpb=c00d0012f5d6aa3987f5465caf8b6ead5ac919ff;p=platform%2Fkernel%2Fu-boot.git diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 8ec2a38..70112c9 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -124,9 +124,7 @@ typedef struct ccsr_i2c { } ccsr_i2c_t; #if defined(CONFIG_ARCH_MPC8540) || \ - defined(CONFIG_ARCH_MPC8541) || \ - defined(CONFIG_ARCH_MPC8548) || \ - defined(CONFIG_ARCH_MPC8555) + defined(CONFIG_ARCH_MPC8548) /* DUART Registers */ typedef struct ccsr_duart { u8 res1[1280]; @@ -272,6 +270,7 @@ typedef struct ccsr_gpio { u32 gpier; u32 gpimr; u32 gpicr; + u32 gpibe; } ccsr_gpio_t; #endif @@ -1785,8 +1784,7 @@ typedef struct ccsr_gur { #define FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII 0x20000000 #define FSL_CORENET_RCWSR13_EC2 0x0c000000 /* bits 420..421 */ #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000 -#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000 -#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII 0x20000000 +#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x04000000 #define FSL_CORENET_RCWSR13_MAC2_GMII_SEL 0x00000080 #define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH 0x00000000 #define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT 0x00000080 @@ -1794,7 +1792,7 @@ typedef struct ccsr_gur { #define PXCKEN_MASK 0x80000000 #define PXCK_MASK 0x00FF0000 #define PXCK_BITS_START 16 -#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023) +#elif defined(CONFIG_ARCH_T1024) #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff800000 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 23 #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000 @@ -1808,7 +1806,7 @@ typedef struct ccsr_gur { #define PXCKEN_MASK 0x80000000 #define PXCK_MASK 0x00FF0000 #define PXCK_BITS_START 16 -#elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081) +#elif defined(CONFIG_ARCH_T2080) #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000 @@ -1853,7 +1851,7 @@ typedef struct ccsr_gur { #define FSL_CORENET_RCWSR11_EC2_USB2 0x00100000 #endif #if defined(CONFIG_ARCH_P2041) || \ - defined(CONFIG_ARCH_P3041) || defined(CONFIG_ARCH_P5020) + defined(CONFIG_ARCH_P3041) #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII 0x00000000 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII 0x00800000 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_NONE 0x00c00000 @@ -1880,7 +1878,7 @@ typedef struct ccsr_gur { #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC6_RGMII 0x08000000 #define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000 #endif -#if defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081) +#if defined(CONFIG_ARCH_T2080) #define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */ #define FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII 0x00000000 #define FSL_CORENET_RCWSR13_EC1_GPIO 0x40000000 @@ -2157,10 +2155,7 @@ typedef struct ccsr_gur { #define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000 #define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000 #define MPC85xx_PORDEVSR_PCI1 0x00800000 -#if defined(CONFIG_ARCH_P1022) -#define MPC85xx_PORDEVSR_IO_SEL 0x007c0000 -#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 18 -#elif defined(CONFIG_ARCH_P1023) +#if defined(CONFIG_ARCH_P1023) #define MPC85xx_PORDEVSR_IO_SEL 0x00600000 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21 #else @@ -2205,15 +2200,8 @@ typedef struct ccsr_gur { u32 gpiocr; /* GPIO control */ #endif u8 res3[12]; -#if defined(CONFIG_ARCH_MPC8569) - u32 plppar1; /* Platform port pin assignment 1 */ - u32 plppar2; /* Platform port pin assignment 2 */ - u32 plpdir1; /* Platform port pin direction 1 */ - u32 plpdir2; /* Platform port pin direction 2 */ -#else u32 gpoutdr; /* General-purpose output data */ u8 res4[12]; -#endif u32 gpindr; /* General-purpose input data */ u8 res5[12]; u32 pmuxcr; /* Alt. function signal multiplex control */ @@ -2285,12 +2273,6 @@ typedef struct ccsr_gur { #define MPC85xx_PMUXCR_QE11 0x00000010 #define MPC85xx_PMUXCR_QE12 0x00000008 #endif -#if defined(CONFIG_ARCH_P1022) -#define MPC85xx_PMUXCR_TDM_MASK 0x0001cc00 -#define MPC85xx_PMUXCR_TDM 0x00014800 -#define MPC85xx_PMUXCR_SPI_MASK 0x00600000 -#define MPC85xx_PMUXCR_SPI 0x00000000 -#endif #if defined(CONFIG_ARCH_BSC9131) #define MPC85xx_PMUXCR_TSEC2_DMA_GPIO_IRQ 0x40000000 #define MPC85xx_PMUXCR_TSEC2_USB 0xC0000000 @@ -2370,10 +2352,6 @@ typedef struct ccsr_gur { #define MPC85xx_PMUXCR2_DEBUG_MUX_SEL_USBPHY 0x00002000 #define MPC85xx_PMUXCR2_PLL_LKDT_EXPOSE 0x00001000 #endif -#if defined(CONFIG_ARCH_P1022) -#define MPC85xx_PMUXCR2_ETSECUSB_MASK 0x001f8000 -#define MPC85xx_PMUXCR2_USB 0x00150000 -#endif #if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132) #if defined(CONFIG_ARCH_BSC9131) #define MPC85xx_PMUXCR2_UART_CTS_B0_SIM_PD 0X40000000 @@ -2479,11 +2457,7 @@ typedef struct ccsr_gur { u32 svr; /* System version */ u8 res10[8]; u32 rstcr; /* Reset control */ -#if defined(CONFIG_ARCH_MPC8568) || defined(CONFIG_ARCH_MPC8569) - u8 res11a[76]; - par_io_t qe_par_io[7]; - u8 res11b[1600]; -#elif defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025) +#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025) u8 res11a[12]; u32 iovselsr; u8 res11b[60]; @@ -2522,7 +2496,7 @@ typedef struct ccsr_gur { #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 #define MAX_SERDES 4 -#if defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023) +#if defined(CONFIG_ARCH_T1024) #define SRDS_MAX_LANES 4 #else #define SRDS_MAX_LANES 8 @@ -2879,7 +2853,7 @@ struct ccsr_pman { #define CONFIG_SYS_MPC85xx_PCIX2_OFFSET 0x9000 #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0xa000 #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x9000 -#if defined(CONFIG_ARCH_MPC8572) || defined(CONFIG_ARCH_P2020) +#if defined(CONFIG_ARCH_P2020) #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x8000 #else #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0xb000