X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=arch%2Fpowerpc%2Finclude%2Fasm%2Fimmap_85xx.h;h=70112c91fc51e09962bd001e053d4f47bc1885db;hb=ed7fe2bee12a464da5b944cc2218d924793b8a80;hp=2e959dd895e1f5af1e8181f471ee22f930386741;hpb=7f825218dc3ca8c4f43ac288d800832d96d455f2;p=platform%2Fkernel%2Fu-boot.git diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 2e959dd..70112c9 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * MPC85xx Internal Memory Map * @@ -5,8 +6,6 @@ * * Copyright(c) 2002,2003 Motorola Inc. * Xianghua Xiao (x.xiao@motorola.com) - * - * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __IMMAP_85xx__ @@ -125,9 +124,7 @@ typedef struct ccsr_i2c { } ccsr_i2c_t; #if defined(CONFIG_ARCH_MPC8540) || \ - defined(CONFIG_MPC8541) || \ - defined(CONFIG_ARCH_MPC8548) || \ - defined(CONFIG_MPC8555) + defined(CONFIG_ARCH_MPC8548) /* DUART Registers */ typedef struct ccsr_duart { u8 res1[1280]; @@ -273,6 +270,7 @@ typedef struct ccsr_gpio { u32 gpier; u32 gpimr; u32 gpicr; + u32 gpibe; } ccsr_gpio_t; #endif @@ -1759,8 +1757,7 @@ typedef struct ccsr_gur { /* use reserved bits 18~23 as scratch space to host DDR PLL ratio */ #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT 8 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f -#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ - defined(CONFIG_PPC_T4080) +#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfc000000 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 26 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000 @@ -1770,14 +1767,13 @@ typedef struct ccsr_gur { #define FSL_CORENET2_RCWSR4_SRDS4_PRTCL 0x000000f8 #define FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT 3 #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000 -#elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) +#elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420) #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfe000000 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 25 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16 #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000 -#elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\ -defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) +#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042) #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000 @@ -1788,17 +1784,15 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII 0x20000000 #define FSL_CORENET_RCWSR13_EC2 0x0c000000 /* bits 420..421 */ #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000 -#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000 -#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII 0x20000000 +#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x04000000 #define FSL_CORENET_RCWSR13_MAC2_GMII_SEL 0x00000080 #define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH 0x00000000 -#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT 0x80000000 +#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT 0x00000080 #define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET 0x28 #define PXCKEN_MASK 0x80000000 #define PXCK_MASK 0x00FF0000 #define PXCK_BITS_START 16 -#elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) || \ - defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) +#elif defined(CONFIG_ARCH_T1024) #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff800000 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 23 #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000 @@ -1812,7 +1806,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define PXCKEN_MASK 0x80000000 #define PXCK_MASK 0x00FF0000 #define PXCK_BITS_START 16 -#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) +#elif defined(CONFIG_ARCH_T2080) #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000 @@ -1848,7 +1842,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000 #define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000 #define FSL_CORENET_RCWSR11_EC1 0x00c00000 /* bits 360..361 */ -#ifdef CONFIG_PPC_P4080 +#ifdef CONFIG_ARCH_P4080 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1 0x00000000 #define FSL_CORENET_RCWSR11_EC1_FM1_USB1 0x00800000 #define FSL_CORENET_RCWSR11_EC2 0x001c0000 /* bits 363..365 */ @@ -1856,8 +1850,8 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2 0x00080000 #define FSL_CORENET_RCWSR11_EC2_USB2 0x00100000 #endif -#if defined(CONFIG_PPC_P2041) \ - || defined(CONFIG_PPC_P3041) || defined(CONFIG_PPC_P5020) +#if defined(CONFIG_ARCH_P2041) || \ + defined(CONFIG_ARCH_P3041) #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII 0x00000000 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII 0x00800000 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_NONE 0x00c00000 @@ -1866,7 +1860,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_MII 0x00100000 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_NONE 0x00180000 #endif -#if defined(CONFIG_PPC_P5040) +#if defined(CONFIG_ARCH_P5040) #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_RGMII 0x00000000 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_MII 0x00800000 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_NONE 0x00c00000 @@ -1875,8 +1869,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII 0x00100000 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE 0x00180000 #endif -#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ - defined(CONFIG_PPC_T4080) +#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) #define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */ #define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000 #define FSL_CORENET_RCWSR13_EC1_FM2_GPIO 0x40000000 @@ -1885,7 +1878,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC6_RGMII 0x08000000 #define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000 #endif -#if defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) +#if defined(CONFIG_ARCH_T2080) #define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */ #define FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII 0x00000000 #define FSL_CORENET_RCWSR13_EC1_GPIO 0x40000000 @@ -2150,7 +2143,7 @@ typedef struct ccsr_gur { #define PORBMSR_ROMLOC_NOR 0xf u32 porimpscr; /* POR I/O impedance status & control */ u32 pordevsr; /* POR I/O device status regsiter */ -#if defined(CONFIG_P1017) || defined(CONFIG_P1023) +#if defined(CONFIG_ARCH_P1023) #define MPC85xx_PORDEVSR_SGMII1_DIS 0x10000000 #define MPC85xx_PORDEVSR_SGMII2_DIS 0x08000000 #define MPC85xx_PORDEVSR_TSEC1_PRTC 0x02000000 @@ -2162,14 +2155,11 @@ typedef struct ccsr_gur { #define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000 #define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000 #define MPC85xx_PORDEVSR_PCI1 0x00800000 -#if defined(CONFIG_P1013) || defined(CONFIG_P1022) -#define MPC85xx_PORDEVSR_IO_SEL 0x007c0000 -#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 18 -#elif defined(CONFIG_P1017) || defined(CONFIG_P1023) +#if defined(CONFIG_ARCH_P1023) #define MPC85xx_PORDEVSR_IO_SEL 0x00600000 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21 #else -#if defined(CONFIG_P1010) +#if defined(CONFIG_ARCH_P1010) #define MPC85xx_PORDEVSR_IO_SEL 0x00600000 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21 #elif defined(CONFIG_ARCH_BSC9132) @@ -2181,7 +2171,7 @@ typedef struct ccsr_gur { #else #define MPC85xx_PORDEVSR_IO_SEL 0x00780000 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 19 -#endif /* if defined(CONFIG_P1010) */ +#endif /* if defined(CONFIG_ARCH_P1010) */ #endif #define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000 #define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000 @@ -2210,19 +2200,12 @@ typedef struct ccsr_gur { u32 gpiocr; /* GPIO control */ #endif u8 res3[12]; -#if defined(CONFIG_MPC8569) - u32 plppar1; /* Platform port pin assignment 1 */ - u32 plppar2; /* Platform port pin assignment 2 */ - u32 plpdir1; /* Platform port pin direction 1 */ - u32 plpdir2; /* Platform port pin direction 2 */ -#else u32 gpoutdr; /* General-purpose output data */ u8 res4[12]; -#endif u32 gpindr; /* General-purpose input data */ u8 res5[12]; u32 pmuxcr; /* Alt. function signal multiplex control */ -#if defined(CONFIG_P1010) || defined(CONFIG_P1014) +#if defined(CONFIG_ARCH_P1010) #define MPC85xx_PMUXCR_TSEC1_0_1588 0x40000000 #define MPC85xx_PMUXCR_TSEC1_0_RES 0xC0000000 #define MPC85xx_PMUXCR_TSEC1_1_1588_TRIG 0x10000000 @@ -2268,7 +2251,7 @@ typedef struct ccsr_gur { #define MPC85xx_PMUXCR_CAN2_TDM 0x00000002 #define MPC85xx_PMUXCR_CAN2_RES 0x00000003 #endif -#if defined(CONFIG_P1017) || defined(CONFIG_P1023) +#if defined(CONFIG_ARCH_P1023) #define MPC85xx_PMUXCR_TSEC1_1 0x10000000 #else #define MPC85xx_PMUXCR_SD_DATA 0x80000000 @@ -2290,12 +2273,6 @@ typedef struct ccsr_gur { #define MPC85xx_PMUXCR_QE11 0x00000010 #define MPC85xx_PMUXCR_QE12 0x00000008 #endif -#if defined(CONFIG_P1013) || defined(CONFIG_P1022) -#define MPC85xx_PMUXCR_TDM_MASK 0x0001cc00 -#define MPC85xx_PMUXCR_TDM 0x00014800 -#define MPC85xx_PMUXCR_SPI_MASK 0x00600000 -#define MPC85xx_PMUXCR_SPI 0x00000000 -#endif #if defined(CONFIG_ARCH_BSC9131) #define MPC85xx_PMUXCR_TSEC2_DMA_GPIO_IRQ 0x40000000 #define MPC85xx_PMUXCR_TSEC2_USB 0xC0000000 @@ -2350,7 +2327,7 @@ typedef struct ccsr_gur { #define MPC85xx_PMUXCR_SPI_GPIO 0x00000100 #endif u32 pmuxcr2; /* Alt. function signal multiplex control 2 */ -#if defined(CONFIG_P1010) || defined(CONFIG_P1014) +#if defined(CONFIG_ARCH_P1010) #define MPC85xx_PMUXCR2_UART_GPIO 0x40000000 #define MPC85xx_PMUXCR2_UART_TDM 0x80000000 #define MPC85xx_PMUXCR2_UART_RES 0xC0000000 @@ -2375,10 +2352,6 @@ typedef struct ccsr_gur { #define MPC85xx_PMUXCR2_DEBUG_MUX_SEL_USBPHY 0x00002000 #define MPC85xx_PMUXCR2_PLL_LKDT_EXPOSE 0x00001000 #endif -#if defined(CONFIG_P1013) || defined(CONFIG_P1022) -#define MPC85xx_PMUXCR2_ETSECUSB_MASK 0x001f8000 -#define MPC85xx_PMUXCR2_USB 0x00150000 -#endif #if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132) #if defined(CONFIG_ARCH_BSC9131) #define MPC85xx_PMUXCR2_UART_CTS_B0_SIM_PD 0X40000000 @@ -2484,11 +2457,7 @@ typedef struct ccsr_gur { u32 svr; /* System version */ u8 res10[8]; u32 rstcr; /* Reset control */ -#if defined(CONFIG_MPC8568)||defined(CONFIG_MPC8569) - u8 res11a[76]; - par_io_t qe_par_io[7]; - u8 res11b[1600]; -#elif defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025) +#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025) u8 res11a[12]; u32 iovselsr; u8 res11b[60]; @@ -2527,7 +2496,11 @@ typedef struct ccsr_gur { #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 #define MAX_SERDES 4 +#if defined(CONFIG_ARCH_T1024) +#define SRDS_MAX_LANES 4 +#else #define SRDS_MAX_LANES 8 +#endif #define SRDS_MAX_BANK 2 typedef struct serdes_corenet { struct { @@ -2702,66 +2675,6 @@ enum { FSL_SRDS_B3_LANE_D = 23, }; -typedef struct ccsr_qman { -#ifdef CONFIG_SYS_FSL_QMAN_V3 - u8 res0[0x200]; -#else - struct { - u32 qcsp_lio_cfg; /* 0x0 - SW Portal n LIO cfg */ - u32 qcsp_io_cfg; /* 0x4 - SW Portal n IO cfg */ - u32 res; - u32 qcsp_dd_cfg; /* 0xc - SW Portal n Dynamic Debug cfg */ - } qcsp[32]; -#endif - /* Not actually reserved, but irrelevant to u-boot */ - u8 res[0xbf8 - 0x200]; - u32 ip_rev_1; - u32 ip_rev_2; - u32 fqd_bare; /* FQD Extended Base Addr Register */ - u32 fqd_bar; /* FQD Base Addr Register */ - u8 res1[0x8]; - u32 fqd_ar; /* FQD Attributes Register */ - u8 res2[0xc]; - u32 pfdr_bare; /* PFDR Extended Base Addr Register */ - u32 pfdr_bar; /* PFDR Base Addr Register */ - u8 res3[0x8]; - u32 pfdr_ar; /* PFDR Attributes Register */ - u8 res4[0x4c]; - u32 qcsp_bare; /* QCSP Extended Base Addr Register */ - u32 qcsp_bar; /* QCSP Base Addr Register */ - u8 res5[0x78]; - u32 ci_sched_cfg; /* Initiator Scheduling Configuration */ - u32 srcidr; /* Source ID Register */ - u32 liodnr; /* LIODN Register */ - u8 res6[4]; - u32 ci_rlm_cfg; /* Initiator Read Latency Monitor Cfg */ - u32 ci_rlm_avg; /* Initiator Read Latency Monitor Avg */ - u8 res7[0x2e8]; -#ifdef CONFIG_SYS_FSL_QMAN_V3 - struct { - u32 qcsp_lio_cfg; /* 0x0 - SW Portal n LIO cfg */ - u32 qcsp_io_cfg; /* 0x4 - SW Portal n IO cfg */ - u32 res; - u32 qcsp_dd_cfg; /* 0xc - SW Portal n Dynamic Debug cfg*/ - } qcsp[50]; -#endif -} ccsr_qman_t; - -typedef struct ccsr_bman { - /* Not actually reserved, but irrelevant to u-boot */ - u8 res[0xbf8]; - u32 ip_rev_1; - u32 ip_rev_2; - u32 fbpr_bare; /* FBPR Extended Base Addr Register */ - u32 fbpr_bar; /* FBPR Base Addr Register */ - u8 res1[0x8]; - u32 fbpr_ar; /* FBPR Attributes Register */ - u8 res2[0xf0]; - u32 srcidr; /* Source ID Register */ - u32 liodnr; /* LIODN Register */ - u8 res7[0x2f4]; -} ccsr_bman_t; - typedef struct ccsr_pme { u8 res0[0x804]; u32 liodnbr; /* LIODN Base Register */ @@ -2883,8 +2796,8 @@ struct ccsr_pman { #define CONFIG_SYS_MPC85xx_TDM_OFFSET 0x185000 #define CONFIG_SYS_MPC85xx_QE_OFFSET 0x140000 #define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000 -#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_PPC_B4860)\ - && !defined(CONFIG_PPC_B4420) +#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_ARCH_B4860) && \ + !defined(CONFIG_ARCH_B4420) #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x240000 #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x250000 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x260000 @@ -2940,7 +2853,7 @@ struct ccsr_pman { #define CONFIG_SYS_MPC85xx_PCIX2_OFFSET 0x9000 #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0xa000 #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x9000 -#if defined(CONFIG_MPC8572) || defined(CONFIG_P2020) +#if defined(CONFIG_ARCH_P2020) #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x8000 #else #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0xb000