X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=arch%2Fpowerpc%2Finclude%2Fasm%2Ffsl_law.h;h=eee78c8856dc5d7994129e8aa69d564a781216d3;hb=e71372cb6371033a762b3329d063c3735a783a76;hp=bea1636768d04ec12bba2d7f2a368c71a9d33618;hpb=5a34d9bf31a021987f97f20aefa812b97b58584e;p=platform%2Fkernel%2Fu-boot.git diff --git a/arch/powerpc/include/asm/fsl_law.h b/arch/powerpc/include/asm/fsl_law.h index bea1636..eee78c8 100644 --- a/arch/powerpc/include/asm/fsl_law.h +++ b/arch/powerpc/include/asm/fsl_law.h @@ -1,15 +1,14 @@ /* * Copyright 2008-2011 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _FSL_LAW_H_ #define _FSL_LAW_H_ #include +#include #define LAW_EN 0x80000000 @@ -68,6 +67,7 @@ enum law_trgt_if { LAW_TRGT_IF_DDR_INTLV_1234 = 0x16, LAW_TRGT_IF_BMAN = 0x18, LAW_TRGT_IF_DCSR = 0x1d, + LAW_TRGT_IF_CCSR = 0x1e, LAW_TRGT_IF_LBC = 0x1f, LAW_TRGT_IF_QMAN = 0x3c, @@ -82,19 +82,24 @@ enum law_trgt_if { #ifndef CONFIG_MPC8641 LAW_TRGT_IF_PCIE_1 = 0x02, #endif -#if defined(CONFIG_BSC9131) +#if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132) LAW_TRGT_IF_OCN_DSP = 0x03, #else -#if !defined(CONFIG_MPC8572) && !defined(CONFIG_P2020) +#if !defined(CONFIG_ARCH_MPC8572) && !defined(CONFIG_ARCH_P2020) LAW_TRGT_IF_PCIE_3 = 0x03, #endif #endif LAW_TRGT_IF_LBC = 0x04, LAW_TRGT_IF_CCSR = 0x08, LAW_TRGT_IF_DSP_CCSR = 0x09, + LAW_TRGT_IF_PLATFORM_SRAM = 0x0a, LAW_TRGT_IF_DDR_INTRLV = 0x0b, LAW_TRGT_IF_RIO = 0x0c, +#if defined(CONFIG_ARCH_BSC9132) + LAW_TRGT_IF_CLASS_DSP = 0x0d, +#else LAW_TRGT_IF_RIO_2 = 0x0d, +#endif LAW_TRGT_IF_DPAA_SWP_SRAM = 0x0e, LAW_TRGT_IF_DDR = 0x0f, LAW_TRGT_IF_DDR_2 = 0x16, /* 2nd controller */ @@ -116,7 +121,7 @@ enum law_trgt_if { #define LAW_TRGT_IF_PCIE_1 LAW_TRGT_IF_PCI #endif -#if defined(CONFIG_MPC8572) || defined(CONFIG_P2020) +#if defined(CONFIG_ARCH_MPC8572) || defined(CONFIG_ARCH_P2020) #define LAW_TRGT_IF_PCIE_3 LAW_TRGT_IF_PCI #endif #endif /* CONFIG_FSL_CORENET */