X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=arch%2Fpowerpc%2Finclude%2Fasm%2Fconfig_mpc85xx.h;h=1d46b1423012a242a6f6752390207f06c8e36a82;hb=fbbbc86e8ebac4f42f4ca39ceba80cea27c983bc;hp=0b9638bceef0bf565610dbaae045aa66de83d86c;hpb=b8715d8def240014da5614a4f940130ec06d9ebf;p=kernel%2Fu-boot.git diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 0b9638b..1d46b14 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -139,6 +139,7 @@ #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY @@ -333,9 +334,10 @@ #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 +#define CONFIG_SYS_FSL_ERRATUM_USB14 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 +#define CONFIG_SYS_FSL_ERRATUM_DDR_A003 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 -#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 @@ -365,9 +367,10 @@ #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 +#define CONFIG_SYS_FSL_ERRATUM_USB14 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 +#define CONFIG_SYS_FSL_ERRATUM_DDR_A003 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 -#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 @@ -409,7 +412,6 @@ #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 -#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 @@ -442,8 +444,9 @@ #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_USB14 +#define CONFIG_SYS_FSL_ERRATUM_DDR_A003 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 -#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 @@ -473,7 +476,7 @@ #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 -#define CONFIG_SYS_FSL_ERRATUM_USB138 +#define CONFIG_SYS_FSL_ERRATUM_USB14 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 #define CONFIG_SYS_FSL_ERRATUM_A004699 @@ -488,29 +491,58 @@ #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 +#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 +#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_NAND_FSL_IFC -#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 -#elif defined(CONFIG_PPC_T4240) +#elif defined(CONFIG_BSC9132) +#define CONFIG_MAX_CPUS 2 +#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 +#define CONFIG_FSL_SDHC_V2_3 +#define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_TSECV2 +#define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_NUM_DDR_CONTROLLERS 2 +#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 +#define CONFIG_NAND_FSL_IFC +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK +#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" + +#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) +#define CONFIG_E6500 #define CONFIG_SYS_PPC64 /* 64-bit core */ #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ +#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ +#ifdef CONFIG_PPC_T4240 #define CONFIG_MAX_CPUS 12 +#define CONFIG_SYS_NUM_FM1_DTSEC 8 +#define CONFIG_SYS_NUM_FM1_10GEC 2 +#define CONFIG_SYS_NUM_FM2_DTSEC 8 +#define CONFIG_SYS_NUM_FM2_10GEC 2 +#define CONFIG_NUM_DDR_CONTROLLERS 3 +#else +#define CONFIG_MAX_CPUS 8 +#define CONFIG_SYS_NUM_FM1_DTSEC 7 +#define CONFIG_SYS_NUM_FM1_10GEC 1 +#define CONFIG_SYS_NUM_FM2_DTSEC 7 +#define CONFIG_SYS_NUM_FM2_10GEC 1 +#define CONFIG_NUM_DDR_CONTROLLERS 2 +#endif #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SRDS_3 #define CONFIG_SYS_FSL_SRDS_4 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_NUM_FMAN 2 -#define CONFIG_SYS_NUM_FM1_DTSEC 8 -#define CONFIG_SYS_NUM_FM1_10GEC 2 -#define CONFIG_SYS_NUM_FM2_DTSEC 8 -#define CONFIG_SYS_NUM_FM2_10GEC 2 -#define CONFIG_NUM_DDR_CONTROLLERS 3 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 +#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_SYS_FMAN_V3 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 #define CONFIG_SYS_FSL_TBCLK_DIV 16 @@ -518,36 +550,80 @@ #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 -#define CONFIG_SYS_FSL_USB1_PHY_ENABLE -#define CONFIG_SYS_FSL_USB2_PHY_ENABLE +#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_A004468 #define CONFIG_SYS_FSL_ERRATUM_A_004934 +#define CONFIG_SYS_FSL_ERRATUM_A005871 +#define CONFIG_SYS_FSL_ERRATUM_A006593 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 +#define CONFIG_SYS_FSL_PCI_VER_3_X -#elif defined(CONFIG_PPC_B4860) +#elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) +#define CONFIG_E6500 #define CONFIG_SYS_PPC64 /* 64-bit core */ #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ -#define CONFIG_MAX_CPUS 4 -#define CONFIG_SYS_FSL_NUM_CC_PLLS 4 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_NUM_FMAN 1 +#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 +#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 +#define CONFIG_SYS_FMAN_V3 +#define CONFIG_SYS_FM_MURAM_SIZE 0x60000 +#define CONFIG_SYS_FSL_TBCLK_DIV 16 +#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" +#define CONFIG_SYS_FSL_USB1_PHY_ENABLE +#define CONFIG_SYS_FSL_ERRATUM_A_004934 +#define CONFIG_SYS_FSL_ERRATUM_A005871 +#define CONFIG_SYS_FSL_ERRATUM_A006593 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 + +#ifdef CONFIG_PPC_B4860 +#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 +#define CONFIG_MAX_CPUS 4 +#define CONFIG_SYS_FSL_NUM_CC_PLLS 4 #define CONFIG_SYS_NUM_FM1_DTSEC 6 #define CONFIG_SYS_NUM_FM1_10GEC 2 +#define CONFIG_NUM_DDR_CONTROLLERS 2 +#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 +#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 +#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 +#else +#define CONFIG_MAX_CPUS 2 +#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2 +#define CONFIG_SYS_FSL_NUM_CC_PLLS 4 +#define CONFIG_SYS_NUM_FM1_DTSEC 4 +#define CONFIG_SYS_NUM_FM1_10GEC 0 +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#endif + +#elif defined(CONFIG_PPC_T1040) +#define CONFIG_E5500 +#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ +#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ +#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 +#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ +#define CONFIG_MAX_CPUS 4 +#define CONFIG_SYS_FSL_NUM_CC_PLLS 5 +#define CONFIG_SYS_FSL_NUM_LAWS 16 +#define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_SYS_NUM_FMAN 1 +#define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 +#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 #define CONFIG_SYS_FMAN_V3 -#define CONFIG_SYS_FM_MURAM_SIZE 0x60000 -#define CONFIG_SYS_FSL_TBCLK_DIV 16 +#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CONFIG_SYS_FSL_TBCLK_DIV 32 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE -#define CONFIG_SYS_FSL_ERRATUM_A_004934 +#define CONFIG_SYS_FSL_USB2_PHY_ENABLE +#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #else @@ -558,4 +634,10 @@ #error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform." #endif +#ifdef CONFIG_E6500 +#define CONFIG_SYS_FSL_THREADS_PER_CORE 2 +#else +#define CONFIG_SYS_FSL_THREADS_PER_CORE 1 +#endif + #endif /* _ASM_MPC85xx_CONFIG_H_ */