X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=arch%2Fpowerpc%2Fcpu%2Fppc4xx%2F40x_spd_sdram.c;h=55a58f6b185d61d94075da73d1b9a94d419c563b;hb=1a4596601fd395f3afb8f82f3f840c5e00bdd57a;hp=f65cd886a51572ce509dff6f7d1716af3e923829;hpb=500fbae2043532275e09a8666d837d052c9bad9a;p=platform%2Fkernel%2Fu-boot.git

diff --git a/arch/powerpc/cpu/ppc4xx/40x_spd_sdram.c b/arch/powerpc/cpu/ppc4xx/40x_spd_sdram.c
index f65cd88..55a58f6 100644
--- a/arch/powerpc/cpu/ppc4xx/40x_spd_sdram.c
+++ b/arch/powerpc/cpu/ppc4xx/40x_spd_sdram.c
@@ -23,29 +23,13 @@
  * (C) Copyright 2005
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:	GPL-2.0+ 
  */
 
 #include <common.h>
 #include <asm/processor.h>
 #include <i2c.h>
-#include <ppc4xx.h>
+#include <asm/ppc4xx.h>
 
 #if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_440)
 
@@ -116,26 +100,25 @@ long int spd_sdram(int(read_spd)(uint addr))
 {
 	int tmp,row,col;
 	int total_size,bank_size,bank_code;
-	int ecc_on;
 	int mode;
 	int bank_cnt;
 
 	int sdram0_pmit=0x07c00000;
+	int sdram0_b0cr;
+	int sdram0_b1cr = 0;
 #ifndef CONFIG_405EP /* not on PPC405EP */
+	int sdram0_b2cr = 0;
+	int sdram0_b3cr = 0;
 	int sdram0_besr0 = -1;
 	int sdram0_besr1 = -1;
 	int sdram0_eccesr = -1;
-#endif
 	int sdram0_ecccfg;
+	int ecc_on;
+#endif
 
 	int sdram0_rtr=0;
 	int sdram0_tr=0;
 
-	int sdram0_b0cr;
-	int sdram0_b1cr;
-	int sdram0_b2cr;
-	int sdram0_b3cr;
-
 	int sdram0_cfg=0;
 
 	int t_rp;
@@ -295,6 +278,7 @@ long int spd_sdram(int(read_spd)(uint addr))
 	if (bank_cnt > 4)	/* we only have 4 banks to work with */
 		SPD_ERR("SDRAM - unsupported module rows for this width\n");
 
+#ifndef CONFIG_405EP /* not on PPC405EP */
 	/* now check for ECC ability of module. We only support ECC
 	 *   on 32 bit wide devices with 8 bit ECC.
 	 */
@@ -305,6 +289,7 @@ long int spd_sdram(int(read_spd)(uint addr))
 		sdram0_ecccfg = 0;
 		ecc_on = 0;
 	}
+#endif
 
 	/*------------------------------------------------------------------
 	 * calculate total size
@@ -378,9 +363,6 @@ long int spd_sdram(int(read_spd)(uint addr))
 	 * using the calculated values, compute the bank
 	 * config register values.
 	 * -------------------------------------------------------------------*/
-	sdram0_b1cr = 0;
-	sdram0_b2cr = 0;
-	sdram0_b3cr = 0;
 
 	/* compute the size of each bank */
 	bank_size = total_size / bank_cnt;
@@ -444,8 +426,10 @@ long int spd_sdram(int(read_spd)(uint addr))
 	/* SDRAM have a power on delay,	 500 micro should do */
 	udelay(500);
 	sdram0_cfg = SDRAM0_CFG_DCE | SDRAM0_CFG_BRPF(1) | SDRAM0_CFG_ECCDD | SDRAM0_CFG_EMDULR;
+#ifndef CONFIG_405EP /* not on PPC405EP */
 	if (ecc_on)
 		sdram0_cfg |= SDRAM0_CFG_MEMCHK;
+#endif
 	mtsdram(SDRAM0_CFG, sdram0_cfg);
 
 	return (total_size);