X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=arch%2Fpowerpc%2Fcpu%2Fmpc8xx%2Ffec.c;h=65dfeabba438f82ce25e4716a7cecf200704bdf8;hb=1a4596601fd395f3afb8f82f3f840c5e00bdd57a;hp=89c1ff939d2a7c7279732b467d79a1c104e1de4b;hpb=9d62f20d0861ef87460d073dc189c851715b46ae;p=platform%2Fkernel%2Fu-boot.git diff --git a/arch/powerpc/cpu/mpc8xx/fec.c b/arch/powerpc/cpu/mpc8xx/fec.c index 89c1ff9..65dfeabb 100644 --- a/arch/powerpc/cpu/mpc8xx/fec.c +++ b/arch/powerpc/cpu/mpc8xx/fec.c @@ -2,23 +2,7 @@ * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -63,9 +47,9 @@ DECLARE_GLOBAL_DATA_PTR; static int mii_discover_phy(struct eth_device *dev); #endif -int fec8xx_miiphy_read(char *devname, unsigned char addr, +int fec8xx_miiphy_read(const char *devname, unsigned char addr, unsigned char reg, unsigned short *value); -int fec8xx_miiphy_write(char *devname, unsigned char addr, +int fec8xx_miiphy_write(const char *devname, unsigned char addr, unsigned char reg, unsigned short value); static struct ether_fcc_info_s @@ -139,7 +123,7 @@ typedef volatile struct CommonBufferDescriptor { static RTXBD *rtx = NULL; -static int fec_send(struct eth_device* dev, volatile void *packet, int length); +static int fec_send(struct eth_device *dev, void *packet, int length); static int fec_recv(struct eth_device* dev); static int fec_init(struct eth_device* dev, bd_t * bd); static void fec_halt(struct eth_device* dev); @@ -164,9 +148,9 @@ int fec_initialize(bd_t *bis) /* for FEC1 make sure that the name of the interface is the same as the old one for compatibility reasons */ if (i == 0) { - sprintf (dev->name, "FEC ETHERNET"); + sprintf (dev->name, "FEC"); } else { - sprintf (dev->name, "FEC%d ETHERNET", + sprintf (dev->name, "FEC%d", ether_fcc_info[i].ether_index + 1); } @@ -193,7 +177,7 @@ int fec_initialize(bd_t *bis) return 1; } -static int fec_send(struct eth_device* dev, volatile void *packet, int length) +static int fec_send(struct eth_device *dev, void *packet, int length) { int j, rc; struct ether_fcc_info_s *efis = dev->priv; @@ -267,14 +251,14 @@ static int fec_recv (struct eth_device *dev) rtx->rxbd[rxIdx].cbd_sc); #endif } else { - volatile uchar *rx = NetRxPackets[rxIdx]; + uchar *rx = NetRxPackets[rxIdx]; length -= 4; #if defined(CONFIG_CMD_CDP) if ((rx[0] & 1) != 0 && memcmp ((uchar *) rx, NetBcastAddr, 6) != 0 - && memcmp ((uchar *) rx, NetCDPAddr, 6) != 0) + && !is_cdp_packet((uchar *)rx)) rx = NULL; #endif /* @@ -378,35 +362,39 @@ static void fec_pin_init(int fecidx) { bd_t *bd = gd->bd; volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile fec_t *fecp; - - /* - * only two FECs please - */ - if ((unsigned int)fecidx >= 2) - hang(); - - if (fecidx == 0) - fecp = &immr->im_cpm.cp_fec1; - else - fecp = &immr->im_cpm.cp_fec2; /* * Set MII speed to 2.5 MHz or slightly below. - * * According to the MPC860T (Rev. D) Fast ethernet controller user - * * manual (6.2.14), - * * the MII management interface clock must be less than or equal - * * to 2.5 MHz. - * * This MDC frequency is equal to system clock / (2 * MII_SPEED). - * * Then MII_SPEED = system_clock / 2 * 2,5 MHz. + * + * According to the MPC860T (Rev. D) Fast ethernet controller user + * manual (6.2.14), + * the MII management interface clock must be less than or equal + * to 2.5 MHz. + * This MDC frequency is equal to system clock / (2 * MII_SPEED). + * Then MII_SPEED = system_clock / 2 * 2,5 MHz. * * All MII configuration is done via FEC1 registers: */ immr->im_cpm.cp_fec1.fec_mii_speed = ((bd->bi_intfreq + 4999999) / 5000000) << 1; #if defined(CONFIG_NETTA) || defined(CONFIG_NETPHONE) || defined(CONFIG_NETTA2) - /* our PHYs are the limit at 2.5 MHz */ - fecp->fec_mii_speed <<= 1; + { + volatile fec_t *fecp; + + /* + * only two FECs please + */ + if ((unsigned int)fecidx >= 2) + hang(); + + if (fecidx == 0) + fecp = &immr->im_cpm.cp_fec1; + else + fecp = &immr->im_cpm.cp_fec2; + + /* our PHYs are the limit at 2.5 MHz */ + fecp->fec_mii_speed <<= 1; + } #endif #if defined(CONFIG_MPC885_FAMILY) && defined(WANT_MII) @@ -456,7 +444,7 @@ static void fec_pin_init(int fecidx) #endif /* !CONFIG_RMII */ -#elif !defined(CONFIG_ICU862) && !defined(CONFIG_IAD210) +#elif !defined(CONFIG_ICU862) /* * Configure all of port D for MII. */ @@ -888,14 +876,14 @@ static int mii_discover_phy(struct eth_device *dev) udelay(10000); /* wait 10ms */ } for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { - phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); + phytype = mii_send(mk_mii_read(phyno, MII_PHYSID2)); #ifdef ET_DEBUG printf("PHY type 0x%x pass %d type ", phytype, pass); #endif if (phytype != 0xffff) { phyaddr = phyno; phytype |= mii_send(mk_mii_read(phyno, - PHY_PHYIDR1)) << 16; + MII_PHYSID1)) << 16; #ifdef ET_DEBUG printf("PHY @ 0x%x pass %d type ",phyno,pass); @@ -990,7 +978,7 @@ void mii_init (void) * Otherwise they hang in mii_send() !!! Sorry! *****************************************************************************/ -int fec8xx_miiphy_read(char *devname, unsigned char addr, +int fec8xx_miiphy_read(const char *devname, unsigned char addr, unsigned char reg, unsigned short *value) { short rdreg; /* register working value */ @@ -1007,14 +995,13 @@ int fec8xx_miiphy_read(char *devname, unsigned char addr, return 0; } -int fec8xx_miiphy_write(char *devname, unsigned char addr, +int fec8xx_miiphy_write(const char *devname, unsigned char addr, unsigned char reg, unsigned short value) { - short rdreg; /* register working value */ #ifdef MII_DEBUG printf ("miiphy_write(0x%x) @ 0x%x = ", reg, addr); #endif - rdreg = mii_send(mk_mii_write(addr, reg, value)); + (void)mii_send(mk_mii_write(addr, reg, value)); #ifdef MII_DEBUG printf ("0x%04x\n", value);