X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=arch%2Fpowerpc%2Fcpu%2Fmpc86xx%2FKconfig;h=1ee87038bed433860ac95c3bff4da8e2cc5012f4;hb=ed7fe2bee12a464da5b944cc2218d924793b8a80;hp=14e8b1aa66a3b25ff8fcdde22c8fa67e03754435;hpb=e38b15b0619f9a8b869896229355808f494fb2ac;p=platform%2Fkernel%2Fu-boot.git

diff --git a/arch/powerpc/cpu/mpc86xx/Kconfig b/arch/powerpc/cpu/mpc86xx/Kconfig
index 14e8b1a..1ee8703 100644
--- a/arch/powerpc/cpu/mpc86xx/Kconfig
+++ b/arch/powerpc/cpu/mpc86xx/Kconfig
@@ -6,24 +6,47 @@ config SYS_CPU
 
 choice
 	prompt "Target select"
+	optional
 
 config TARGET_SBC8641D
 	bool "Support sbc8641d"
-
-config TARGET_MPC8610HPCD
-	bool "Support MPC8610HPCD"
-
-config TARGET_MPC8641HPCN
-	bool "Support MPC8641HPCN"
-
-config TARGET_XPEDITE517X
-	bool "Support xpedite517x"
+	select ARCH_MPC8641
+	select BOARD_EARLY_INIT_F
 
 endchoice
 
-source "board/freescale/mpc8610hpcd/Kconfig"
-source "board/freescale/mpc8641hpcn/Kconfig"
+config ARCH_MPC8610
+	bool
+	select FSL_LAW
+	select SYS_FSL_HAS_DDR1
+	select SYS_FSL_HAS_DDR2
+
+config ARCH_MPC8641
+	bool
+	select FSL_LAW
+	select SYS_FSL_HAS_DDR1
+	select SYS_FSL_HAS_DDR2
+
+config FSL_LAW
+	bool
+	help
+		Use Freescale common code for Local Access Window
+
+config SYS_CCSRBAR_DEFAULT
+	hex "Default CCSRBAR address"
+	default 0xff700000 if ARCH_MPC8610 || ARCH_MPC8641
+	help
+		Default value of CCSRBAR comes from power-on-reset. It
+		is fixed on each SoC. Some SoCs can have different value
+		if changed by pre-boot regime. The value here must match
+		the current value in SoC. If not sure, do not change.
+config SYS_FSL_NUM_LAWS
+	int "Number of local access windows"
+	default 10 if ARCH_MPC8610 || ARCH_MPC8641
+	help
+		Number of local access windows. This is fixed per SoC.
+		If not sure, do not change.
+
 source "board/sbc8641d/Kconfig"
-source "board/xes/xpedite517x/Kconfig"
 
 endmenu