X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=arch%2Fpowerpc%2Fcpu%2Fmpc85xx%2FKconfig;h=d01e69bf892edfa4fc14c4f8fc5505e2c54655be;hb=4143a237947576b581eed1eaf88c207df80d418e;hp=4471754d026402e8ca18e50839a6d20c3301ef06;hpb=111a8b57354bb5aff55635502a0cdf74cb63e835;p=platform%2Fkernel%2Fu-boot.git diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 4471754..d01e69b 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -12,6 +12,59 @@ config CMD_ERRATA This enables the 'errata' command which displays a list of errata work-arounds which are enabled for the current board. +config FSL_PREPBL_ESDHC_BOOT_SECTOR + bool "Generate QorIQ pre-PBL eSDHC boot sector" + depends on MPC85xx + depends on SYS_EXTRA_OPTIONS = SDCARD + help + With this option final image would have prepended QorIQ pre-PBL eSDHC + boot sector suitable for SD card images. This boot sector instruct + BootROM to configure L2 SRAM and eSDHC then load image from SD card + into L2 SRAM and finally jump to image entry point. + + This is alternative to Freescale boot_format tool, but works only for + SD card images and only for L2 SRAM booting. U-Boot images generated + with this option should not passed to boot_format tool. + + For other configuration like booting from eSPI or configuring SDRAM + please use Freescale boot_format tool without this option. See file + doc/README.mpc85xx-sd-spi-boot + +config FSL_PREPBL_ESDHC_BOOT_SECTOR_START + int "QorIQ pre-PBL eSDHC boot sector start offset" + depends on FSL_PREPBL_ESDHC_BOOT_SECTOR + range 0 23 + default 0 + help + QorIQ pre-PBL eSDHC boot sector may be located on one of the first + 24 SD card sectors. Select SD card sector on which final U-Boot + image (with this boot sector) would be installed. + + By default first SD card sector (0) is used. But this may be changed + to allow installing U-Boot image on some partition (with fixed start + sector). + + Please note that any sector on SD card prior this boot sector must + not contain ASCII "BOOT" bytes at sector offset 0x40. + +config FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA + int "Relative data sector for QorIQ pre-PBL eSDHC boot sector" + depends on FSL_PREPBL_ESDHC_BOOT_SECTOR + default 1 + range 1 8388607 + help + Select data sector from the beginning of QorIQ pre-PBL eSDHC boot + sector on which would be stored raw U-Boot image. + + By default is it second sector (1) which is the first available free + sector (on the first sector is stored boot sector). It can be any + sector number which offset in bytes can be expressed by 32-bit number. + + In case this final U-Boot image (with this boot sector) is put on + the FAT32 partition into reserved boot area, this data sector needs + to be at least 2 (third sector) because FAT32 use second sector for + its data. + choice prompt "Target select" optional @@ -101,6 +154,7 @@ config TARGET_P2041RDB bool "Support P2041RDB" select ARCH_P2041 select BOARD_LATE_INIT if CHAIN_OF_TRUST + select FSL_CORENET select PHYS_64BIT imply CMD_SATA imply FSL_SATA @@ -109,6 +163,7 @@ config TARGET_QEMU_PPCE500 bool "Support qemu-ppce500" select ARCH_QEMU_E500 select PHYS_64BIT + select SYS_RAMBOOT imply OF_HAS_PRIOR_STAGE config TARGET_T1024RDB @@ -179,6 +234,7 @@ config TARGET_KMP204X config TARGET_KMCENT2 bool "Support kmcent2" select VENDOR_KM + select FSL_CORENET endchoice @@ -186,7 +242,9 @@ config ARCH_B4420 bool select E500MC select E6500 + select FSL_CORENET select FSL_LAW + select HETROGENOUS_CLUSTERS select SYS_FSL_DDR_VER_47 select SYS_FSL_ERRATUM_A004477 select SYS_FSL_ERRATUM_A005871 @@ -195,12 +253,13 @@ config ARCH_B4420 select SYS_FSL_ERRATUM_A006475 select SYS_FSL_ERRATUM_A006593 select SYS_FSL_ERRATUM_A007075 - select SYS_FSL_ERRATUM_A007186 + select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST select SYS_FSL_ERRATUM_A007212 select SYS_FSL_ERRATUM_A009942 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_QORIQ_CHASSIS2 + select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select SYS_PPC64 @@ -213,7 +272,9 @@ config ARCH_B4860 bool select E500MC select E6500 + select FSL_CORENET select FSL_LAW + select HETROGENOUS_CLUSTERS select SYS_FSL_DDR_VER_47 select SYS_FSL_ERRATUM_A004477 select SYS_FSL_ERRATUM_A005871 @@ -222,13 +283,14 @@ config ARCH_B4860 select SYS_FSL_ERRATUM_A006475 select SYS_FSL_ERRATUM_A006593 select SYS_FSL_ERRATUM_A007075 - select SYS_FSL_ERRATUM_A007186 + select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST select SYS_FSL_ERRATUM_A007212 select SYS_FSL_ERRATUM_A007907 select SYS_FSL_ERRATUM_A009942 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_QORIQ_CHASSIS2 + select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select SYS_PPC64 @@ -266,6 +328,7 @@ config ARCH_BSC9132 select FSL_PCIE_RESET select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC + select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select SYS_PPC_E500_USE_DEBUG_TLB @@ -317,6 +380,7 @@ config ARCH_MPC8540 config ARCH_MPC8544 bool + select BTB select FSL_LAW select SYS_CACHE_SHIFT_5 select SYS_FSL_ERRATUM_A005125 @@ -330,6 +394,7 @@ config ARCH_MPC8544 config ARCH_MPC8548 bool + select BTB select FSL_LAW select SYS_FSL_ERRATUM_A005125 select SYS_FSL_ERRATUM_NMG_DDR120 @@ -352,6 +417,8 @@ config ARCH_MPC8560 config ARCH_P1010 bool + select A003399_NOR_WORKAROUND if SYS_FSL_ERRATUM_IFC_A003399 && !SPL + select BTB select FSL_LAW select SYS_CACHE_SHIFT_5 select SYS_HAS_SERDES @@ -370,6 +437,7 @@ config ARCH_P1010 select FSL_PCIE_RESET select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC + select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select SYS_PPC_E500_USE_DEBUG_TLB @@ -381,6 +449,7 @@ config ARCH_P1010 imply CMD_PCI imply CMD_REGINFO imply FSL_SATA + imply TIMESTAMP config ARCH_P1011 bool @@ -399,6 +468,7 @@ config ARCH_P1011 config ARCH_P1020 bool + select BTB select FSL_LAW select SYS_CACHE_SHIFT_5 select SYS_FSL_ERRATUM_A004508 @@ -449,6 +519,7 @@ config ARCH_P1023 select FSL_PCIE_RESET select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC + select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select FSL_ELBC @@ -495,6 +566,7 @@ config ARCH_P1025 config ARCH_P2020 bool + select BTB select FSL_LAW select SYS_CACHE_SHIFT_5 select SYS_FSL_ERRATUM_A004477 @@ -512,9 +584,11 @@ config ARCH_P2020 imply CMD_EEPROM imply CMD_NAND imply CMD_REGINFO + imply TIMESTAMP config ARCH_P2041 bool + select BACKSIDE_L2_CACHE select E500MC select FSL_LAW select SYS_CACHE_SHIFT_6 @@ -533,6 +607,7 @@ config ARCH_P2041 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_QORIQ_CHASSIS1 + select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select FSL_ELBC @@ -540,7 +615,9 @@ config ARCH_P2041 config ARCH_P3041 bool + select BACKSIDE_L2_CACHE select E500MC + select FSL_CORENET select FSL_LAW select SYS_CACHE_SHIFT_6 select SYS_FSL_DDR_VER_44 @@ -560,6 +637,7 @@ config ARCH_P3041 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_QORIQ_CHASSIS1 + select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select FSL_ELBC @@ -570,7 +648,9 @@ config ARCH_P3041 config ARCH_P4080 bool + select BACKSIDE_L2_CACHE select E500MC + select FSL_CORENET select FSL_LAW select SYS_CACHE_SHIFT_6 select SYS_FSL_DDR_VER_44 @@ -591,6 +671,7 @@ config ARCH_P4080 select SYS_FSL_ERRATUM_I2C_A004447 select SYS_FSL_ERRATUM_NMG_CPU_A011 select SYS_FSL_ERRATUM_SRIO_A004034 + select SYS_FSL_PCIE_COMPAT_P4080_PCIE select SYS_P4080_ERRATUM_CPU22 select SYS_P4080_ERRATUM_PCIE_A003 select SYS_P4080_ERRATUM_SERDES8 @@ -609,7 +690,9 @@ config ARCH_P4080 config ARCH_P5040 bool + select BACKSIDE_L2_CACHE select E500MC + select FSL_CORENET select FSL_LAW select SYS_CACHE_SHIFT_6 select SYS_FSL_DDR_VER_44 @@ -625,6 +708,7 @@ config ARCH_P5040 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_QORIQ_CHASSIS1 + select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select SYS_PPC64 @@ -639,7 +723,10 @@ config ARCH_QEMU_E500 config ARCH_T1024 bool + select BACKSIDE_L2_CACHE select E500MC + select E5500 + select FSL_CORENET select FSL_LAW select SYS_CACHE_SHIFT_6 select SYS_FSL_DDR_VER_50 @@ -652,6 +739,7 @@ config ARCH_T1024 select SYS_FSL_HAS_DDR4 select SYS_FSL_HAS_SEC select SYS_FSL_QORIQ_CHASSIS2 + select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_5 select FSL_IFC @@ -662,7 +750,10 @@ config ARCH_T1024 config ARCH_T1040 bool + select BACKSIDE_L2_CACHE select E500MC + select E5500 + select FSL_CORENET select FSL_LAW select SYS_CACHE_SHIFT_6 select SYS_FSL_DDR_VER_50 @@ -676,6 +767,7 @@ config ARCH_T1040 select SYS_FSL_HAS_DDR4 select SYS_FSL_HAS_SEC select SYS_FSL_QORIQ_CHASSIS2 + select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_5 select FSL_IFC @@ -685,7 +777,10 @@ config ARCH_T1040 config ARCH_T1042 bool + select BACKSIDE_L2_CACHE select E500MC + select E5500 + select FSL_CORENET select FSL_LAW select SYS_CACHE_SHIFT_6 select SYS_FSL_DDR_VER_50 @@ -699,6 +794,7 @@ config ARCH_T1042 select SYS_FSL_HAS_DDR4 select SYS_FSL_HAS_SEC select SYS_FSL_QORIQ_CHASSIS2 + select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_5 select FSL_IFC @@ -710,12 +806,13 @@ config ARCH_T2080 bool select E500MC select E6500 + select FSL_CORENET select FSL_LAW select SYS_CACHE_SHIFT_6 select SYS_FSL_DDR_VER_47 select SYS_FSL_ERRATUM_A006379 select SYS_FSL_ERRATUM_A006593 - select SYS_FSL_ERRATUM_A007186 + select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST select SYS_FSL_ERRATUM_A007212 select SYS_FSL_ERRATUM_A007815 select SYS_FSL_ERRATUM_A007907 @@ -726,6 +823,7 @@ config ARCH_T2080 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_QORIQ_CHASSIS2 + select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select SYS_PPC64 @@ -740,6 +838,7 @@ config ARCH_T4240 bool select E500MC select E6500 + select FSL_CORENET select FSL_LAW select SYS_CACHE_SHIFT_6 select SYS_FSL_DDR_VER_47 @@ -748,7 +847,7 @@ config ARCH_T4240 select SYS_FSL_ERRATUM_A006261 select SYS_FSL_ERRATUM_A006379 select SYS_FSL_ERRATUM_A006593 - select SYS_FSL_ERRATUM_A007186 + select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST select SYS_FSL_ERRATUM_A007798 select SYS_FSL_ERRATUM_A007815 select SYS_FSL_ERRATUM_A007907 @@ -757,6 +856,7 @@ config ARCH_T4240 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_QORIQ_CHASSIS2 + select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select SYS_PPC64 @@ -770,6 +870,9 @@ config MPC85XX_HAVE_RESET_VECTOR bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc" depends on MPC85xx +config BTB + bool "toggle branch predition" + config BOOKE bool default y @@ -782,12 +885,17 @@ config E500 config E500MC bool + select BTB imply CMD_PCI help Enble PowerPC E500MC core +config E5500 + bool + config E6500 bool + select BTB help Enable PowerPC E6500 core @@ -796,11 +904,8 @@ config FSL_LAW help Use Freescale common code for Local Access Window -config NXP_ESBC - bool "NXP_ESBC" - help - Enable Freescale Secure Boot feature. Normally selected - by defconfig. If unsure, do not change. +config HETROGENOUS_CLUSTERS + bool config MAX_CPUS int "Maximum number of CPUs permitted for MPC85xx" @@ -866,6 +971,18 @@ config SYS_CCSRBAR_DEFAULT if changed by pre-boot regime. The value here must match the current value in SoC. If not sure, do not change. +config A003399_NOR_WORKAROUND + bool + help + Enables a workaround for IFC erratum A003399. It is only required + during NOR boot. + +config A008044_WORKAROUND + bool + help + Enables a workaround for T1040/T1042 erratum A008044. It is only + required during NAND boot and valid for Rev 1.0 SoC revision + config SYS_FSL_ERRATUM_A004468 bool @@ -948,6 +1065,7 @@ config SYS_FSL_ERRATUM_A007907 config SYS_FSL_ERRATUM_A008044 bool + select A008044_WORKAROUND if MTD_RAW_NAND config SYS_FSL_ERRATUM_CPC_A002 bool @@ -1069,8 +1187,16 @@ config SYS_FSL_NUM_LAWS Number of local access windows. This is fixed per SoC. If not sure, do not change. +config SYS_FSL_CORES_PER_CLUSTER + int + depends on SYS_FSL_QORIQ_CHASSIS2 + default 4 if ARCH_B4860 || ARCH_T2080 || ARCH_T4240 + default 2 if ARCH_B4420 + default 1 if ARCH_T1024 || ARCH_T1040 || ARCH_T1042 + config SYS_FSL_THREADS_PER_CORE int + depends on SYS_FSL_QORIQ_CHASSIS2 default 2 if E6500 default 1 @@ -1082,6 +1208,38 @@ config SYS_NUM_TLBCAMS Number of TLB CAM entries for Book-E chips. 64 for E500MC, 16 for other E500 SoCs. +if HETROGENOUS_CLUSTERS + +config SYS_MAPLE + def_bool y + +config SYS_CPRI + def_bool y + +config PPC_CLUSTER_START + int + default 0 + +config DSP_CLUSTER_START + int + default 1 + +config SYS_CPRI_CLK + int + default 3 + +config SYS_ULB_CLK + int + default 4 + +config SYS_ETVPE_CLK + int + default 1 +endif + +config BACKSIDE_L2_CACHE + bool + config SYS_PPC64 bool @@ -1143,6 +1301,75 @@ config SYS_FSL_LBC_CLK_DIV Defines divider of platform clock(clock input to eLBC controller). +config ENABLE_36BIT_PHYS + bool "Enable 36bit physical address space support" + +config SYS_BOOK3E_HV + bool "Category E.HV is supported" + depends on BOOKE + +config FSL_CORENET + bool + select SYS_FSL_CPC + +config SYS_CPC_REINIT_F + bool + help + The CPC is configured as SRAM at the time of U-Boot entry and is + required to be re-initialized. + +config SYS_FSL_CPC + bool + +config SYS_CACHE_STASHING + bool "Enable cache stashing" + +config SYS_FSL_PCIE_COMPAT_P4080_PCIE + bool + +config SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22 + bool + +config SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24 + bool + +config SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30 + bool + +config SYS_FSL_PCIE_COMPAT + string + depends on FSL_CORENET + default "fsl,p4080-pcie" if SYS_FSL_PCIE_COMPAT_P4080_PCIE + default "fsl,qoriq-pcie-v2.2" if SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22 + default "fsl,qoriq-pcie-v2.4" if SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24 + default "fsl,qoriq-pcie-v3.0" if SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30 + help + Defines the string to utilize when trying to match PCIe device tree + nodes for the given platform. + +config SYS_MPC85XX_NO_RESETVEC + bool "Discard resetvec section and move bootpg section up" + depends on MPC85xx + help + If this variable is specified, the section .resetvec is not kept and + the section .bootpg is placed in the previous 4k of the .text section. + +config SPL_SYS_MPC85XX_NO_RESETVEC + bool "Discard resetvec section and move bootpg section up, in SPL" + depends on MPC85xx && SPL + help + If this variable is specified, the section .resetvec is not kept and + the section .bootpg is placed in the previous 4k of the .text section, + of the SPL portion of the binary. + +config TPL_SYS_MPC85XX_NO_RESETVEC + bool "Discard resetvec section and move bootpg section up, in TPL" + depends on MPC85xx && TPL + help + If this variable is specified, the section .resetvec is not kept and + the section .bootpg is placed in the previous 4k of the .text section, + of the SPL portion of the binary. + config FSL_VIA bool @@ -1157,7 +1384,6 @@ source "board/freescale/t104xrdb/Kconfig" source "board/freescale/t208xqds/Kconfig" source "board/freescale/t208xrdb/Kconfig" source "board/freescale/t4rdb/Kconfig" -source "board/keymile/Kconfig" source "board/socrates/Kconfig" endmenu