X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=arch%2Fpowerpc%2Fcpu%2Fmpc83xx%2Fstart.S;h=d2fced8aba86130351bf34539fbc01f4ace56fbd;hb=19d1f1a2f3ccfbf85125150f7876ce22714b38bd;hp=a9acb83f0b1cdd4fb55a5375ca6f3b06a6e5f60f;hpb=39768f7715ed637ef02f49fc7de664cc1aaf14b3;p=platform%2Fkernel%2Fu-boot.git diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S index a9acb83..d2fced8a 100644 --- a/arch/powerpc/cpu/mpc83xx/start.S +++ b/arch/powerpc/cpu/mpc83xx/start.S @@ -4,23 +4,7 @@ * Copyright (C) 2000, 2001,2002 Wolfgang Denk * Copyright Freescale Semiconductor, Inc. 2004, 2006, 2008. * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -30,11 +14,9 @@ #include #include #include -#include #include #define CONFIG_83XX 1 /* needed for Linux kernel header files*/ -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ #include #include @@ -43,10 +25,6 @@ #include #include -#ifndef CONFIG_IDENT_STRING -#define CONFIG_IDENT_STRING "MPC83XX" -#endif - /* We don't want the MMU yet. */ #undef MSR_KERNEL @@ -60,7 +38,13 @@ #define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI) #endif -#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_NAND_SPL) || \ + (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)) +#define MINIMAL_SPL +#endif + +#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NAND_SPL) && \ + !defined(CONFIG_SYS_RAMBOOT) #define CONFIG_SYS_FLASHBOOT #endif @@ -72,9 +56,9 @@ START_GOT GOT_ENTRY(_GOT2_TABLE_) GOT_ENTRY(__bss_start) - GOT_ENTRY(__bss_end__) + GOT_ENTRY(__bss_end) -#ifndef CONFIG_NAND_SPL +#ifndef MINIMAL_SPL GOT_ENTRY(_FIXUP_TABLE_) GOT_ENTRY(_start) GOT_ENTRY(_start_of_vectors) @@ -107,9 +91,7 @@ .globl version_string version_string: - .ascii U_BOOT_VERSION - .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" - .ascii " ", CONFIG_IDENT_STRING, "\0" + .ascii U_BOOT_VERSION_STRING, "\0" .align 2 @@ -134,11 +116,6 @@ disable_addr_trans: mtspr SRR1, r3 rfi - .globl get_pvr -get_pvr: - mfspr r3, PVR - blr - .globl ppcDWstore ppcDWstore: lfd 1, 0(r4) @@ -153,7 +130,7 @@ ppcDWload: #ifndef CONFIG_DEFAULT_IMMR #error CONFIG_DEFAULT_IMMR must be defined -#endif /* CONFIG_SYS_DEFAULT_IMMR */ +#endif /* CONFIG_DEFAULT_IMMR */ #ifndef CONFIG_SYS_IMMR #define CONFIG_SYS_IMMR CONFIG_DEFAULT_IMMR #endif /* CONFIG_SYS_IMMR */ @@ -210,7 +187,8 @@ _start: /* time t 0 */ /* Initialise the E300 processor core */ /*------------------------------------------*/ -#ifdef CONFIG_NAND_SPL +#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MPC83XX_WAIT_FOR_NAND)) || \ + defined(CONFIG_NAND_SPL) /* The FCM begins execution after only the first page * is loaded. Wait for the rest before branching * to another flash page. @@ -270,14 +248,40 @@ in_flash: #endif /* set up the stack pointer in our newly created - * cache-ram (r1) */ - lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h - ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l + * cache-ram; use r3 to keep the new SP for now to + * avoid overiding the SP it uselessly */ + lis r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h + ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l + + /* r4 = end of GD area */ + addi r4, r3, GENERATED_GBL_DATA_SIZE + + /* Zero GD area */ + li r0, 0 +1: + subi r4, r4, 1 + stb r0, 0(r4) + cmplw r3, r4 + bne 1b +#if CONFIG_VAL(SYS_MALLOC_F_LEN) + +#if CONFIG_VAL(SYS_MALLOC_F_LEN) + GENERATED_GBL_DATA_SIZE > CONFIG_SYS_INIT_RAM_SIZE +#error "SYS_MALLOC_F_LEN too large to fit into initial RAM." +#endif + + /* r3 = new stack pointer / pre-reloc malloc area */ + subi r3, r3, CONFIG_VAL(SYS_MALLOC_F_LEN) + + /* Set pointer to pre-reloc malloc area in GD */ + stw r3, GD_MALLOC_BASE(r4) +#endif li r0, 0 /* Make room for stack frame header and */ - stwu r0, -4(r1) /* clear final stack frame so that */ - stwu r0, -4(r1) /* stack backtraces terminate cleanly */ + stwu r0, -4(r3) /* clear final stack frame so that */ + stwu r0, -4(r3) /* stack backtraces terminate cleanly */ + /* Finally, actually set SP */ + mr r1, r3 /* let the C-code set up the rest */ /* */ @@ -285,22 +289,19 @@ in_flash: /*------------------------------------------------------*/ GET_GOT /* initialize GOT access */ -#if defined(__pic__) && __pic__ == 1 - /* Needed for upcoming -msingle-pic-base */ - bl _GLOBAL_OFFSET_TABLE_@local-4 - mflr r30 -#endif + /* r3: IMMR */ lis r3, CONFIG_SYS_IMMR@h /* run low-level CPU init code (in Flash)*/ bl cpu_init_f /* run 1st part of board init code (in Flash)*/ + li r3, 0 /* clear boot_flag for calling board_init_f */ bl board_init_f /* NOTREACHED - board_init_f() does not return */ -#ifndef CONFIG_NAND_SPL +#ifndef MINIMAL_SPL /* * Vector Table */ @@ -475,7 +476,7 @@ int_return: lwz r1,GPR1(r1) SYNC rfi -#endif /* !CONFIG_NAND_SPL */ +#endif /* !MINIMAL_SPL */ /* * This code initialises the E300 processor core @@ -732,7 +733,7 @@ setup_bats: * Note: requires that all cache bits in * HID0 are in the low half word. */ -#ifndef CONFIG_NAND_SPL +#ifndef MINIMAL_SPL .globl icache_enable icache_enable: mfspr r3, HID0 @@ -761,7 +762,7 @@ icache_status: mfspr r3, HID0 rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31 blr -#endif /* !CONFIG_NAND_SPL */ +#endif /* !MINIMAL_SPL */ .globl dcache_enable dcache_enable: @@ -826,11 +827,6 @@ relocate_code: mr r10, r5 /* Save copy of Destination Address */ GET_GOT -#if defined(__pic__) && __pic__ == 1 - /* Needed for upcoming -msingle-pic-base */ - bl _GLOBAL_OFFSET_TABLE_@local-4 - mflr r30 -#endif mr r3, r5 /* Destination Address */ lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ ori r4, r4, CONFIG_SYS_MONITOR_BASE@l @@ -949,7 +945,7 @@ in_ram: stw r0,0(r3) 2: bdnz 1b -#ifndef CONFIG_NAND_SPL +#ifndef MINIMAL_SPL /* * Now adjust the fixups and the pointers to the fixups * in case we need to move ourselves again. @@ -976,18 +972,7 @@ clear_bss: * Now clear BSS segment */ lwz r3,GOT(__bss_start) -#if defined(CONFIG_HYMOD) - /* - * For HYMOD - the environment is the very last item in flash. - * The real .bss stops just before environment starts, so only - * clear up to that point. - * - * taken from mods for FADS board - */ - lwz r4,GOT(environment) -#else - lwz r4,GOT(__bss_end__) -#endif + lwz r4,GOT(__bss_end) cmplw 0, r3, r4 beq 6f @@ -1004,7 +989,7 @@ clear_bss: mr r4, r10 /* Destination Address */ bl board_init_r -#ifndef CONFIG_NAND_SPL +#ifndef MINIMAL_SPL /* * Copy exception vector code to low memory * @@ -1074,7 +1059,7 @@ trap_init: mtlr r4 /* restore link register */ blr -#endif /* !CONFIG_NAND_SPL */ +#endif /* !MINIMAL_SPL */ #ifdef CONFIG_SYS_INIT_RAM_LOCK lock_ram_in_cache: @@ -1098,7 +1083,7 @@ lock_ram_in_cache: sync blr -#ifndef CONFIG_NAND_SPL +#ifndef MINIMAL_SPL .globl unlock_ram_in_cache unlock_ram_in_cache: /* invalidate the INIT_RAM section */ @@ -1124,7 +1109,7 @@ unlock_ram_in_cache: sync mtspr HID0, r3 /* no invalidate, unlock */ blr -#endif /* !CONFIG_NAND_SPL */ +#endif /* !MINIMAL_SPL */ #endif /* CONFIG_SYS_INIT_RAM_LOCK */ #ifdef CONFIG_SYS_FLASHBOOT