X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=arch%2Fnios2%2Fcpu%2Fcpu.c;h=85544503a5ee38da46f640c3b4cf25d4d821124b;hb=aa6e94deabb45154cea07ad44c4a5c047bca078b;hp=39ae97221c2a95f2b2395f4ac74318b9e6203f70;hpb=57cfeb5140642b1071b01a7cc5c34d4ef3166180;p=platform%2Fkernel%2Fu-boot.git

diff --git a/arch/nios2/cpu/cpu.c b/arch/nios2/cpu/cpu.c
index 39ae972..8554450 100644
--- a/arch/nios2/cpu/cpu.c
+++ b/arch/nios2/cpu/cpu.c
@@ -1,60 +1,167 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
  * Scott McNutt <smcnutt@psyent.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
-#include <asm/nios2.h>
+#include <command.h>
+#include <cpu.h>
+#include <cpu_func.h>
+#include <dm.h>
+#include <errno.h>
+#include <event.h>
+#include <init.h>
+#include <irq_func.h>
 #include <asm/cache.h>
+#include <asm/global_data.h>
+#include <asm/system.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#if defined (CONFIG_SYS_NIOS_SYSID_BASE)
-extern void display_sysid (void);
-#endif /* CONFIG_SYS_NIOS_SYSID_BASE */
-
 #ifdef CONFIG_DISPLAY_CPUINFO
 int print_cpuinfo(void)
 {
-	printf ("CPU   : Nios-II\n");
-#if !defined(CONFIG_SYS_NIOS_SYSID_BASE)
-	printf ("SYSID : <unknown>\n");
-#else
-	display_sysid ();
-#endif
-	return (0);
+	printf("CPU:   Nios-II\n");
+	return 0;
 }
 #endif /* CONFIG_DISPLAY_CPUINFO */
 
-int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+#ifdef CONFIG_ALTERA_SYSID
+int checkboard(void)
+{
+	display_sysid();
+	return 0;
+}
+#endif
+
+int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 {
 	disable_interrupts();
 	/* indirect call to go beyond 256MB limitation of toolchain */
-	nios2_callr(CONFIG_SYS_RESET_ADDR);
+	nios2_callr(gd->arch.reset_addr);
 	return 0;
 }
 
-int dcache_status(void)
+/*
+ * COPY EXCEPTION TRAMPOLINE -- copy the tramp to the
+ * exception address. Define CONFIG_ROM_STUBS to prevent
+ * the copy (e.g. exception in flash or in other
+ * softare/firmware component).
+ */
+#ifndef CONFIG_ROM_STUBS
+static void copy_exception_trampoline(void)
 {
-	return 1;
+	extern int _except_start, _except_end;
+	void *except_target = (void *)gd->arch.exception_addr;
+
+	if (&_except_start != except_target) {
+		memcpy(except_target, &_except_start,
+		       &_except_end - &_except_start);
+		flush_cache(gd->arch.exception_addr,
+			    &_except_end - &_except_start);
+	}
+}
+#endif
+
+static int nios_cpu_setup(void *ctx, struct event *event)
+{
+	struct udevice *dev;
+	int ret;
+
+	ret = uclass_first_device_err(UCLASS_CPU, &dev);
+	if (ret)
+		return ret;
+
+	gd->ram_size = CFG_SYS_SDRAM_SIZE;
+#ifndef CONFIG_ROM_STUBS
+	copy_exception_trampoline();
+#endif
+
+	return 0;
 }
+EVENT_SPY(EVT_DM_POST_INIT, nios_cpu_setup);
 
-void dcache_enable(void)
+static int altera_nios2_get_desc(const struct udevice *dev, char *buf,
+				 int size)
 {
-	flush_dcache(CONFIG_SYS_DCACHE_SIZE, CONFIG_SYS_DCACHELINE_SIZE);
+	const char *cpu_name = "Nios-II";
+
+	if (size < strlen(cpu_name))
+		return -ENOSPC;
+	strcpy(buf, cpu_name);
+
+	return 0;
 }
 
-void dcache_disable(void)
+static int altera_nios2_get_info(const struct udevice *dev,
+				 struct cpu_info *info)
 {
-	flush_dcache(CONFIG_SYS_DCACHE_SIZE, CONFIG_SYS_DCACHELINE_SIZE);
+	info->cpu_freq = gd->cpu_clk;
+	info->features = (1 << CPU_FEAT_L1_CACHE) |
+		(gd->arch.has_mmu ? (1 << CPU_FEAT_MMU) : 0);
+
+	return 0;
 }
 
-int arch_cpu_init(void)
+static int altera_nios2_get_count(const struct udevice *dev)
 {
-	gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
-	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+	return 1;
+}
 
+static int altera_nios2_probe(struct udevice *dev)
+{
+	const void *blob = gd->fdt_blob;
+	int node = dev_of_offset(dev);
+
+	gd->cpu_clk = fdtdec_get_int(blob, node,
+		"clock-frequency", 0);
+	gd->arch.dcache_line_size = fdtdec_get_int(blob, node,
+		"dcache-line-size", 0);
+	gd->arch.icache_line_size = fdtdec_get_int(blob, node,
+		"icache-line-size", 0);
+	gd->arch.dcache_size = fdtdec_get_int(blob, node,
+		"dcache-size", 0);
+	gd->arch.icache_size = fdtdec_get_int(blob, node,
+		"icache-size", 0);
+	gd->arch.reset_addr = fdtdec_get_int(blob, node,
+		"altr,reset-addr", 0);
+	gd->arch.exception_addr = fdtdec_get_int(blob, node,
+		"altr,exception-addr", 0);
+	gd->arch.has_initda = fdtdec_get_int(blob, node,
+		"altr,has-initda", 0);
+	gd->arch.has_mmu = fdtdec_get_int(blob, node,
+		"altr,has-mmu", 0);
+	gd->arch.io_region_base = gd->arch.has_mmu ? 0xe0000000 : 0x80000000;
+	gd->arch.mem_region_base = gd->arch.has_mmu ? 0xc0000000 : 0x00000000;
+	gd->arch.physaddr_mask = gd->arch.has_mmu ? 0x1fffffff : 0x7fffffff;
+
+	return 0;
+}
+
+static const struct cpu_ops altera_nios2_ops = {
+	.get_desc	= altera_nios2_get_desc,
+	.get_info	= altera_nios2_get_info,
+	.get_count	= altera_nios2_get_count,
+};
+
+static const struct udevice_id altera_nios2_ids[] = {
+	{ .compatible = "altr,nios2-1.0" },
+	{ .compatible = "altr,nios2-1.1" },
+	{ }
+};
+
+U_BOOT_DRIVER(altera_nios2) = {
+	.name		= "altera_nios2",
+	.id		= UCLASS_CPU,
+	.of_match	= altera_nios2_ids,
+	.probe		= altera_nios2_probe,
+	.ops		= &altera_nios2_ops,
+	.flags		= DM_FLAG_PRE_RELOC,
+};
+
+/* This is a dummy function on nios2 */
+int dram_init(void)
+{
 	return 0;
 }