X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=arch%2Farm%2Fmach-tegra%2Fboard.c;h=f8fc042a1dcc273a1f3967f2073b00f9981cfe30;hb=83d290c56fab2d38cd1ab4c4cc7099559c1d5046;hp=b6a84a577478a11374ad3e46ed75bc2c437f59ea;hpb=09f455dca74973ef5e42311162c8dff7e83d44a2;p=platform%2Fkernel%2Fu-boot.git

diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c
index b6a84a5..f8fc042 100644
--- a/arch/arm/mach-tegra/board.c
+++ b/arch/arm/mach-tegra/board.c
@@ -1,21 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
- *  (C) Copyright 2010-2014
+ *  (C) Copyright 2010-2015
  *  NVIDIA Corporation <www.nvidia.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
+#include <dm.h>
+#include <ns16550.h>
+#include <spl.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/funcmux.h>
 #include <asm/arch/mc.h>
 #include <asm/arch/tegra.h>
+#include <asm/arch-tegra/ap.h>
 #include <asm/arch-tegra/board.h>
 #include <asm/arch-tegra/pmc.h>
 #include <asm/arch-tegra/sys_proto.h>
 #include <asm/arch-tegra/warmboot.h>
 
+void save_boot_params_ret(void);
+
 DECLARE_GLOBAL_DATA_PTR;
 
 enum {
@@ -28,27 +33,87 @@ enum {
 	UART_COUNT = 5,
 };
 
+static bool from_spl __attribute__ ((section(".data")));
+
+#ifndef CONFIG_SPL_BUILD
+void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
+{
+	from_spl = r0 != UBOOT_NOT_LOADED_FROM_SPL;
+	save_boot_params_ret();
+}
+#endif
+
+bool spl_was_boot_source(void)
+{
+	return from_spl;
+}
+
+#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
+#if !defined(CONFIG_TEGRA124)
+#error tegra_cpu_is_non_secure has only been validated on Tegra124
+#endif
+bool tegra_cpu_is_non_secure(void)
+{
+	/*
+	 * This register reads 0xffffffff in non-secure mode. This register
+	 * only implements bits 31:20, so the lower bits will always read 0 in
+	 * secure mode. Thus, the lower bits are an indicator for secure vs.
+	 * non-secure mode.
+	 */
+	struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
+	uint32_t mc_s_cfg0 = readl(&mc->mc_security_cfg0);
+	return (mc_s_cfg0 & 1) == 1;
+}
+#endif
+
 /* Read the RAM size directly from the memory controller */
-unsigned int query_sdram_size(void)
+static phys_size_t query_sdram_size(void)
 {
 	struct mc_ctlr *const mc = (struct mc_ctlr *)NV_PA_MC_BASE;
-	u32 size_mb;
+	u32 emem_cfg;
+	phys_size_t size_bytes;
 
-	size_mb = readl(&mc->mc_emem_cfg);
+	emem_cfg = readl(&mc->mc_emem_cfg);
 #if defined(CONFIG_TEGRA20)
-	debug("mc->mc_emem_cfg (MEM_SIZE_KB) = 0x%08x\n", size_mb);
-	size_mb = get_ram_size((void *)PHYS_SDRAM_1, size_mb * 1024);
+	debug("mc->mc_emem_cfg (MEM_SIZE_KB) = 0x%08x\n", emem_cfg);
+	size_bytes = get_ram_size((void *)PHYS_SDRAM_1, emem_cfg * 1024);
 #else
-	debug("mc->mc_emem_cfg (MEM_SIZE_MB) = 0x%08x\n", size_mb);
-	size_mb = get_ram_size((void *)PHYS_SDRAM_1, size_mb * 1024 * 1024);
+	debug("mc->mc_emem_cfg (MEM_SIZE_MB) = 0x%08x\n", emem_cfg);
+#ifndef CONFIG_PHYS_64BIT
+	/*
+	 * If >=4GB RAM is present, the byte RAM size won't fit into 32-bits
+	 * and will wrap. Clip the reported size to the maximum that a 32-bit
+	 * variable can represent (rounded to a page).
+	 */
+	if (emem_cfg >= 4096) {
+		size_bytes = U32_MAX & ~(0x1000 - 1);
+	} else
+#endif
+	{
+		/* RAM size EMC is programmed to. */
+		size_bytes = (phys_size_t)emem_cfg * 1024 * 1024;
+#ifndef CONFIG_ARM64
+		/*
+		 * If all RAM fits within 32-bits, it can be accessed without
+		 * LPAE, so go test the RAM size. Otherwise, we can't access
+		 * all the RAM, and get_ram_size() would get confused, so
+		 * avoid using it. There's no reason we should need this
+		 * validation step anyway.
+		 */
+		if (emem_cfg <= (0 - PHYS_SDRAM_1) / (1024 * 1024))
+			size_bytes = get_ram_size((void *)PHYS_SDRAM_1,
+						  size_bytes);
+#endif
+	}
 #endif
 
 #if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114)
 	/* External memory limited to 2047 MB due to IROM/HI-VEC */
-	if (size_mb == SZ_2G) size_mb -= SZ_1M;
+	if (size_bytes == SZ_2G)
+		size_bytes -= SZ_1M;
 #endif
 
-	return size_mb;
+	return size_bytes;
 }
 
 int dram_init(void)
@@ -58,14 +123,6 @@ int dram_init(void)
 	return 0;
 }
 
-#ifdef CONFIG_DISPLAY_BOARDINFO
-int checkboard(void)
-{
-	printf("Board: %s\n", sysinfo.board_string);
-	return 0;
-}
-#endif	/* CONFIG_DISPLAY_BOARDINFO */
-
 static int uart_configs[] = {
 #if defined(CONFIG_TEGRA20)
  #if defined(CONFIG_TEGRA_UARTA_UAA_UAB)
@@ -93,12 +150,18 @@ static int uart_configs[] = {
 	-1,
 	FUNCMUX_UART4_GMI,	/* UARTD */
 	-1,
-#else	/* Tegra124 */
+#elif defined(CONFIG_TEGRA124)
 	FUNCMUX_UART1_KBC,	/* UARTA */
 	-1,
 	-1,
 	FUNCMUX_UART4_GPIO,	/* UARTD */
 	-1,
+#else	/* Tegra210 */
+	FUNCMUX_UART1_UART1,	/* UARTA */
+	-1,
+	-1,
+	FUNCMUX_UART4_UART4,	/* UARTD */
+	-1,
 #endif
 };
 
@@ -150,7 +213,20 @@ void board_init_uart_f(void)
 	setup_uarts(uart_ids);
 }
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(OF_CONTROL)
+static struct ns16550_platdata ns16550_com1_pdata = {
+	.base = CONFIG_SYS_NS16550_COM1,
+	.reg_shift = 2,
+	.clock = CONFIG_SYS_NS16550_CLK,
+	.fcr = UART_FCR_DEFVAL,
+};
+
+U_BOOT_DEVICE(ns16550_com1) = {
+	"ns16550_serial", &ns16550_com1_pdata
+};
+#endif
+
+#if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
 void enable_caches(void)
 {
 	/* Enable D-cache. I-cache is already enabled in start.S */