X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=arch%2Farm%2Fmach-socfpga%2Fspl_s10.c;h=955a1161e898a0d77ed44ec75a8611a2ac826516;hb=401d1c4f5d2d29c4bc4beaec95402ca23eb63295;hp=69d6e919aa078760b540c8bf7151f94c2982eafb;hpb=914bb7ea2f9373fa59285ff77a95df73848c8f66;p=platform%2Fkernel%2Fu-boot.git diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c index 69d6e91..955a116 100644 --- a/arch/arm/mach-socfpga/spl_s10.c +++ b/arch/arm/mach-socfpga/spl_s10.c @@ -4,6 +4,10 @@ * */ +#include +#include +#include +#include #include #include #include @@ -12,18 +16,16 @@ #include #include #include -#include +#include #include +#include #include -#include #include #include +#include DECLARE_GLOBAL_DATA_PTR; -static struct socfpga_system_manager *sysmgr_regs = - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; - u32 spl_boot_device(void) { /* TODO: Get from SDM or handoff */ @@ -31,9 +33,9 @@ u32 spl_boot_device(void) } #ifdef CONFIG_SPL_MMC_SUPPORT -u32 spl_boot_mode(const u32 boot_device) +u32 spl_mmc_boot_mode(const u32 boot_device) { -#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) +#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4) return MMCSD_MODE_FS; #else return MMCSD_MODE_RAW; @@ -41,89 +43,22 @@ u32 spl_boot_mode(const u32 boot_device) } #endif -void spl_disable_firewall_l4_per(void) -{ - const struct socfpga_firwall_l4_per *firwall_l4_per_base = - (struct socfpga_firwall_l4_per *)SOCFPGA_FIREWALL_L4_PER; - u32 i; - const u32 *addr[] = { - &firwall_l4_per_base->nand, - &firwall_l4_per_base->nand_data, - &firwall_l4_per_base->usb0, - &firwall_l4_per_base->usb1, - &firwall_l4_per_base->spim0, - &firwall_l4_per_base->spim1, - &firwall_l4_per_base->emac0, - &firwall_l4_per_base->emac1, - &firwall_l4_per_base->emac2, - &firwall_l4_per_base->sdmmc, - &firwall_l4_per_base->gpio0, - &firwall_l4_per_base->gpio1, - &firwall_l4_per_base->i2c0, - &firwall_l4_per_base->i2c1, - &firwall_l4_per_base->i2c2, - &firwall_l4_per_base->i2c3, - &firwall_l4_per_base->i2c4, - &firwall_l4_per_base->timer0, - &firwall_l4_per_base->timer1, - &firwall_l4_per_base->uart0, - &firwall_l4_per_base->uart1 - }; - - /* - * The following lines of code will enable non-secure access - * to nand, usb, spi, emac, sdmmc, gpio, i2c, timers and uart. This - * is needed as most OS run in non-secure mode. Thus we need to - * enable non-secure access to these peripherals in order for the - * OS to use these peripherals. - */ - for (i = 0; i < ARRAY_SIZE(addr); i++) - writel(FIREWALL_L4_DISABLE_ALL, addr[i]); -} - -void spl_disable_firewall_l4_sys(void) -{ - const struct socfpga_firwall_l4_sys *firwall_l4_sys_base = - (struct socfpga_firwall_l4_sys *)SOCFPGA_FIREWALL_L4_SYS; - u32 i; - const u32 *addr[] = { - &firwall_l4_sys_base->dma_ecc, - &firwall_l4_sys_base->emac0rx_ecc, - &firwall_l4_sys_base->emac0tx_ecc, - &firwall_l4_sys_base->emac1rx_ecc, - &firwall_l4_sys_base->emac1tx_ecc, - &firwall_l4_sys_base->emac2rx_ecc, - &firwall_l4_sys_base->emac2tx_ecc, - &firwall_l4_sys_base->nand_ecc, - &firwall_l4_sys_base->nand_read_ecc, - &firwall_l4_sys_base->nand_write_ecc, - &firwall_l4_sys_base->ocram_ecc, - &firwall_l4_sys_base->sdmmc_ecc, - &firwall_l4_sys_base->usb0_ecc, - &firwall_l4_sys_base->usb1_ecc, - &firwall_l4_sys_base->clock_manager, - &firwall_l4_sys_base->io_manager, - &firwall_l4_sys_base->reset_manager, - &firwall_l4_sys_base->system_manager, - &firwall_l4_sys_base->watchdog0, - &firwall_l4_sys_base->watchdog1, - &firwall_l4_sys_base->watchdog2, - &firwall_l4_sys_base->watchdog3 - }; - - for (i = 0; i < ARRAY_SIZE(addr); i++) - writel(FIREWALL_L4_DISABLE_ALL, addr[i]); -} - void board_init_f(ulong dummy) { const struct cm_config *cm_default_cfg = cm_get_default_config(); int ret; -#ifdef CONFIG_HW_WATCHDOG + ret = spl_early_init(); + if (ret) + hang(); + + socfpga_get_managers_addr(); + /* Ensure watchdog is paused when debugging is happening */ - writel(SYSMGR_WDDBG_PAUSE_ALL_CPU, &sysmgr_regs->wddbg); + writel(SYSMGR_WDDBG_PAUSE_ALL_CPU, + socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG); +#ifdef CONFIG_HW_WATCHDOG /* Enable watchdog before initializing the HW */ socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1); socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0); @@ -136,7 +71,7 @@ void board_init_f(ulong dummy) socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0); timer_init(); - populate_sysmgr_pinmux(); + sysmgr_pinmux_init(); /* configuring the HPS clocks */ cm_basic_init(cm_default_cfg); @@ -145,29 +80,12 @@ void board_init_f(ulong dummy) socfpga_per_reset(SOCFPGA_RESET(UART0), 0); debug_uart_init(); #endif - ret = spl_early_init(); - if (ret) { - debug("spl_early_init() failed: %d\n", ret); - hang(); - } preloader_console_init(); + print_reset_info(); cm_print_clock_quick_summary(); - /* enable non-secure interface to DMA330 DMA and peripherals */ - writel(SYSMGR_DMA_IRQ_NS | SYSMGR_DMA_MGR_NS, &sysmgr_regs->dma); - writel(SYSMGR_DMAPERIPH_ALL_NS, &sysmgr_regs->dma_periph); - - spl_disable_firewall_l4_per(); - - spl_disable_firewall_l4_sys(); - - /* disable lwsocf2fpga and soc2fpga bridge security */ - writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_SOC2FPGA); - writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_LWSOC2FPGA); - - /* disable SMMU security */ - writel(FIREWALL_L4_DISABLE_ALL, SOCFPGA_FIREWALL_TCU); + firewall_setup(); /* disable ocram security at CCU for non secure access */ clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADMASK_MEM_RAM0), @@ -175,22 +93,15 @@ void board_init_f(ulong dummy) clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADMASK_MEM_RAM0), CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK); - debug("DDR: Initializing Hard Memory Controller\n"); - if (sdram_mmr_init_full(0)) { - puts("DDR: Initialization failed.\n"); - hang(); - } - - gd->ram_size = sdram_calculate_size(); - printf("DDR: %d MiB\n", (int)(gd->ram_size >> 20)); +#if CONFIG_IS_ENABLED(ALTERA_SDRAM) + struct udevice *dev; - /* Sanity check ensure correct SDRAM size specified */ - debug("DDR: Running SDRAM size sanity check\n"); - if (get_ram_size(0, gd->ram_size) != gd->ram_size) { - puts("DDR: SDRAM size check failed!\n"); - hang(); - } - debug("DDR: SDRAM size check passed!\n"); + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + debug("DRAM init failed: %d\n", ret); + hang(); + } +#endif mbox_init();