X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=arch%2Farm%2Fmach-socfpga%2Finclude%2Fmach%2Fsdram.h;h=a58872c3d92f7dbb18344958cc5b2498f7bda672;hb=83d290c56fab2d38cd1ab4c4cc7099559c1d5046;hp=eb409348c37e4257d31855d93351fed4a2c66b32;hpb=d718a26b0c2b6ee869070386fea0ad68a3031987;p=platform%2Fkernel%2Fu-boot.git

diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h b/arch/arm/mach-socfpga/include/mach/sdram.h
index eb40934..a58872c 100644
--- a/arch/arm/mach-socfpga/include/mach/sdram.h
+++ b/arch/arm/mach-socfpga/include/mach/sdram.h
@@ -1,7 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright Altera Corporation (C) 2014-2015
- *
- * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef	_SDRAM_H_
 #define	_SDRAM_H_
@@ -17,6 +16,8 @@ const struct socfpga_sdram_config *socfpga_get_sdram_config(void);
 void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem);
 void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem);
 const struct socfpga_sdram_rw_mgr_config *socfpga_get_sdram_rwmgr_config(void);
+const struct socfpga_sdram_io_config *socfpga_get_sdram_io_config(void);
+const struct socfpga_sdram_misc_config *socfpga_get_sdram_misc_config(void);
 
 #define SDR_CTRLGRP_ADDRESS	(SOCFPGA_SDR_ADDRESS | 0x5000)
 
@@ -28,7 +29,8 @@ struct socfpga_sdr_ctrl {
 	u32	dram_timing4;	/* 0x10 */
 	u32	lowpwr_timing;
 	u32	dram_odt;
-	u32	__padding0[4];
+	u32	extratime1;
+	u32	__padding0[3];
 	u32	dram_addrw;	/* 0x2c */
 	u32	dram_if_width;	/* 0x30 */
 	u32	dram_dev_width;
@@ -86,6 +88,7 @@ struct socfpga_sdram_config {
 	u32	dram_timing4;
 	u32	lowpwr_timing;
 	u32	dram_odt;
+	u32	extratime1;
 	u32	dram_addrw;
 	u32	dram_if_width;
 	u32	dram_dev_width;
@@ -180,6 +183,40 @@ struct socfpga_sdram_rw_mgr_config {
 	u8	mem_virtual_groups_per_write_dqs;
 };
 
+struct socfpga_sdram_io_config {
+	u16	delay_per_opa_tap;
+	u8	delay_per_dchain_tap;
+	u8	delay_per_dqs_en_dchain_tap;
+	u8	dll_chain_length;
+	u8	dqdqs_out_phase_max;
+	u8	dqs_en_delay_max;
+	u8	dqs_en_delay_offset;
+	u8	dqs_en_phase_max;
+	u8	dqs_in_delay_max;
+	u8	dqs_in_reserve;
+	u8	dqs_out_reserve;
+	u8	io_in_delay_max;
+	u8	io_out1_delay_max;
+	u8	io_out2_delay_max;
+	u8	shift_dqs_en_when_shift_dqs;
+};
+
+struct socfpga_sdram_misc_config {
+	u32	reg_file_init_seq_signature;
+	u8	afi_rate_ratio;
+	u8	calib_lfifo_offset;
+	u8	calib_vfifo_offset;
+	u8	enable_super_quick_calibration;
+	u8	max_latency_count_width;
+	u8	read_valid_fifo_size;
+	u8	tinit_cntr0_val;
+	u8	tinit_cntr1_val;
+	u8	tinit_cntr2_val;
+	u8	treset_cntr0_val;
+	u8	treset_cntr1_val;
+	u8	treset_cntr2_val;
+};
+
 #define SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB 23
 #define SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK 0x00800000
 #define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB 22
@@ -391,6 +428,10 @@ SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK \
 /* Field instance: sdr::ctrlgrp::dramsts                                   */
 #define SDR_CTRLGRP_DRAMSTS_DBEERR_MASK 0x00000008
 #define SDR_CTRLGRP_DRAMSTS_SBEERR_MASK 0x00000004
+/* Register template: sdr::ctrlgrp::extratime1                             */
+#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB 20
+#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB 24
+#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB 28
 
 /* SDRAM width macro for configuration with ECC */
 #define SDRAM_WIDTH_32BIT_WITH_ECC	40