X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=arch%2Farm%2Fmach-omap2%2Fclock36xx.c;h=8f3bf4e509082fad0dcb412a0a21573b68e4a485;hb=25f4214e388dda818765b670fb608f2e6467d877;hp=0c5e25ed8879cb1e311905269a5486a35b0b2a70;hpb=b74b953b998bcc2db91b694446f3a2619ec32de6;p=platform%2Fadaptation%2Frenesas_rcar%2Frenesas_kernel.git diff --git a/arch/arm/mach-omap2/clock36xx.c b/arch/arm/mach-omap2/clock36xx.c index 0c5e25e..8f3bf4e 100644 --- a/arch/arm/mach-omap2/clock36xx.c +++ b/arch/arm/mach-omap2/clock36xx.c @@ -22,8 +22,6 @@ #include #include -#include - #include "clock.h" #include "clock36xx.h" @@ -39,34 +37,32 @@ * (Any other value different from the Read value) to the * corresponding CM_CLKSEL register will refresh the dividers. */ -static int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk *clk) +int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *clk) { + struct clk_hw_omap *parent; + struct clk_hw *parent_hw; u32 dummy_v, orig_v, clksel_shift; int ret; /* Clear PWRDN bit of HSDIVIDER */ ret = omap2_dflt_clk_enable(clk); + parent_hw = __clk_get_hw(__clk_get_parent(clk->clk)); + parent = to_clk_hw_omap(parent_hw); + /* Restore the dividers */ if (!ret) { - clksel_shift = __ffs(clk->parent->clksel_mask); - orig_v = __raw_readl(clk->parent->clksel_reg); + clksel_shift = __ffs(parent->clksel_mask); + orig_v = __raw_readl(parent->clksel_reg); dummy_v = orig_v; /* Write any other value different from the Read value */ dummy_v ^= (1 << clksel_shift); - __raw_writel(dummy_v, clk->parent->clksel_reg); + __raw_writel(dummy_v, parent->clksel_reg); /* Write the original divider */ - __raw_writel(orig_v, clk->parent->clksel_reg); + __raw_writel(orig_v, parent->clksel_reg); } return ret; } - -const struct clkops clkops_omap36xx_pwrdn_with_hsdiv_wait_restore = { - .enable = omap36xx_pwrdn_clk_enable_with_hsdiv_restore, - .disable = omap2_dflt_clk_disable, - .find_companion = omap2_clk_dflt_find_companion, - .find_idlest = omap2_clk_dflt_find_idlest, -};