X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=arch%2Farm%2Fmach-mvebu%2Finclude%2Fmach%2Fsoc.h;h=e6383d4a86e2ee6a884a7028523ca11488b432ff;hb=65cc0e2a65d2c9f107b2f42db6396d9ade6c5ad8;hp=0900e4008c12ec3489c0b5357c43ada791cce711;hpb=43ade93bdb0c8bd57382be810a05b3793749ce85;p=platform%2Fkernel%2Fu-boot.git diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index 0900e40..e6383d4 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -1,16 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * (C) Copyright 2009 * Marvell Semiconductor * Written-by: Prafulla Wadaskar * * Header file for the Marvell's Feroceon CPU core. - * - * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _MVEBU_SOC_H #define _MVEBU_SOC_H +#ifndef __ASSEMBLY__ +#include +#endif + #define SOC_MV78230_ID 0x7823 #define SOC_MV78260_ID 0x7826 #define SOC_MV78460_ID 0x7846 @@ -18,6 +21,9 @@ #define SOC_88F6810_ID 0x6810 #define SOC_88F6820_ID 0x6820 #define SOC_88F6828_ID 0x6828 +#define SOC_98DX3236_ID 0xf410 +#define SOC_98DX3336_ID 0xf400 +#define SOC_98DX4251_ID 0xfc00 /* A375 revisions */ #define MV_88F67XX_A0_ID 0x3 @@ -25,11 +31,7 @@ /* A38x revisions */ #define MV_88F68XX_Z1_ID 0x0 #define MV_88F68XX_A0_ID 0x4 - -/* TCLK Core Clock definition */ -#ifndef CONFIG_SYS_TCLK -#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ -#endif +#define MV_88F68XX_B0_ID 0xa /* SOC specific definations */ #define INTREG_BASE 0xd0000000 @@ -52,7 +54,7 @@ #define MVEBU_SDRAM_SCRATCH (MVEBU_REGISTER(0x01504)) #define MVEBU_L2_CACHE_BASE (MVEBU_REGISTER(0x08000)) -#define CONFIG_SYS_PL310_BASE MVEBU_L2_CACHE_BASE +#define CFG_SYS_PL310_BASE MVEBU_L2_CACHE_BASE #define MVEBU_TWSI_BASE (MVEBU_REGISTER(0x11000)) #define MVEBU_TWSI1_BASE (MVEBU_REGISTER(0x11100)) #define MVEBU_MPP_BASE (MVEBU_REGISTER(0x18000)) @@ -73,7 +75,11 @@ #define MVEBU_NAND_BASE (MVEBU_REGISTER(0xd0000)) #define MVEBU_SDIO_BASE (MVEBU_REGISTER(0xd8000)) #define MVEBU_LCD_BASE (MVEBU_REGISTER(0xe0000)) +#ifdef CONFIG_ARMADA_MSYS +#define MVEBU_DFX_BASE (MBUS_DFX_BASE) +#else #define MVEBU_DFX_BASE (MVEBU_REGISTER(0xe4000)) +#endif #define SOC_COHERENCY_FABRIC_CTRL_REG (MVEBU_REGISTER(0x20200)) #define MBUS_ERR_PROP_EN (1 << 8) @@ -93,9 +99,20 @@ #define SPI_PUP_EN BIT(5) #define MVEBU_CORE_DIV_CLK_CTRL(i) (MVEBU_CLOCK_BASE + ((i) * 0x8)) +#ifdef CONFIG_ARMADA_MSYS +#define MVEBU_DFX_DIV_CLK_CTRL(i) (MVEBU_DFX_BASE + 0xf8000 + 0x250 + ((i) * 0x4)) +#define NAND_ECC_DIVCKL_RATIO_OFFS 6 +#define NAND_ECC_DIVCKL_RATIO_MASK (0xF << NAND_ECC_DIVCKL_RATIO_OFFS) +#else #define MVEBU_DFX_DIV_CLK_CTRL(i) (MVEBU_DFX_BASE + 0x250 + ((i) * 0x4)) +#endif +#ifdef CONFIG_ARMADA_MSYS +#define NAND_ECC_DIVCKL_RATIO_OFFS 6 +#define NAND_ECC_DIVCKL_RATIO_MASK (0xF << NAND_ECC_DIVCKL_RATIO_OFFS) +#else #define NAND_ECC_DIVCKL_RATIO_OFFS 8 #define NAND_ECC_DIVCKL_RATIO_MASK (0x3F << NAND_ECC_DIVCKL_RATIO_OFFS) +#endif #define SDRAM_MAX_CS 4 #define SDRAM_ADDR_MASK 0xFF000000 @@ -108,10 +125,12 @@ #define COMPHY_REFCLK_ALIGNMENT (MVEBU_REGISTER(0x182f8)) /* BootROM error register (also includes some status infos) */ -#define CONFIG_BOOTROM_ERR_REG (MVEBU_REGISTER(0x182d0)) +#define BOOTROM_ERR_REG (MVEBU_REGISTER(0x182d0)) #define BOOTROM_ERR_MODE_OFFS 28 #define BOOTROM_ERR_MODE_MASK (0xf << BOOTROM_ERR_MODE_OFFS) #define BOOTROM_ERR_MODE_UART 0x6 +#define BOOTROM_ERR_CODE_OFFS 0 +#define BOOTROM_ERR_CODE_MASK (0xf << BOOTROM_ERR_CODE_OFFS) #if defined(CONFIG_ARMADA_375) /* SAR values for Armada 375 */ @@ -126,6 +145,9 @@ #define BOOT_FROM_UART 0x30 #define BOOT_FROM_SPI 0x38 + +#define CFG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(20)) ? \ + 200000000 : 166000000) #elif defined(CONFIG_ARMADA_38X) /* SAR values for Armada 38x */ #define CONFIG_SAR_REG (MVEBU_REGISTER(0x18600)) @@ -138,11 +160,36 @@ #define BOOT_DEV_SEL_OFFS 4 #define BOOT_DEV_SEL_MASK (0x3f << BOOT_DEV_SEL_OFFS) +#define BOOT_FROM_NAND 0x0A +#define BOOT_FROM_SATA 0x22 #define BOOT_FROM_UART 0x28 +#define BOOT_FROM_SATA_ALT 0x2A +#define BOOT_FROM_UART_ALT 0x3f #define BOOT_FROM_SPI 0x32 #define BOOT_FROM_MMC 0x30 #define BOOT_FROM_MMC_ALT 0x31 -#else + +#define CFG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(15)) ? \ + 200000000 : 250000000) +#elif defined(CONFIG_ARMADA_MSYS) +/* SAR values for MSYS */ +#define CONFIG_SAR_REG (MBUS_DFX_BASE + 0xf8200) +#define CONFIG_SAR2_REG (MBUS_DFX_BASE + 0xf8204) + +#define SAR_CPU_FREQ_OFFS 18 +#define SAR_CPU_FREQ_MASK (0x7 << SAR_CPU_FREQ_OFFS) +#define SAR_BOOT_DEVICE_OFFS 11 +#define SAR_BOOT_DEVICE_MASK (0x7 << SAR_BOOT_DEVICE_OFFS) + +#define BOOT_DEV_SEL_OFFS 11 +#define BOOT_DEV_SEL_MASK (0x7 << BOOT_DEV_SEL_OFFS) + +#define BOOT_FROM_NAND 0x1 +#define BOOT_FROM_UART 0x2 +#define BOOT_FROM_SPI 0x3 + +#define CFG_SYS_TCLK 200000000 /* 200MHz */ +#elif defined(CONFIG_ARMADA_XP) /* SAR values for Armada XP */ #define CONFIG_SAR_REG (MVEBU_REGISTER(0x18230)) #define CONFIG_SAR2_REG (MVEBU_REGISTER(0x18234)) @@ -161,6 +208,8 @@ #define BOOT_FROM_UART 0x2 #define BOOT_FROM_SPI 0x3 + +#define CFG_SYS_TCLK 250000000 /* 250MHz */ #endif #endif /* _MVEBU_SOC_H */