X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=arch%2Farm%2Fmach-imx%2Fmx7%2Fclock.c;h=88f6fe0274829ea7eec14742bd3a83fe91e12494;hb=6cc04547cb3bbd3a3d78947f200acbae19e3c67f;hp=8cda71cf55bee61738a406b9034ff76c9897bc09;hpb=e8f80a5a58c9b506453cc0780687e8ed457d30a6;p=platform%2Fkernel%2Fu-boot.git

diff --git a/arch/arm/mach-imx/mx7/clock.c b/arch/arm/mach-imx/mx7/clock.c
index 8cda71c..88f6fe0 100644
--- a/arch/arm/mach-imx/mx7/clock.c
+++ b/arch/arm/mach-imx/mx7/clock.c
@@ -7,7 +7,11 @@
  */
 
 #include <common.h>
+#include <clock_legacy.h>
+#include <command.h>
 #include <div64.h>
+#include <log.h>
+#include <asm/global_data.h>
 #include <asm/io.h>
 #include <linux/errno.h>
 #include <asm/arch/imx-regs.h>
@@ -19,16 +23,16 @@ struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *)
 					 ANATOP_BASE_ADDR;
 struct mxc_ccm_reg *ccm_reg = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 DECLARE_GLOBAL_DATA_PTR;
 #endif
 
 int get_clocks(void)
 {
-#ifdef CONFIG_FSL_ESDHC
-#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
+#ifdef CONFIG_FSL_ESDHC_IMX
+#if CFG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
 	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
-#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
+#elif CFG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
 	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 #else
 	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
@@ -53,7 +57,7 @@ static u32 get_ipg_clk(void)
 
 u32 imx_get_uartclk(void)
 {
-	return get_root_clk(UART1_CLK_ROOT);
+	return get_root_clk(UART_CLK_ROOT);
 }
 
 u32 imx_get_fecclk(void)
@@ -913,7 +917,7 @@ void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq)
 		}
 
 		if (5 == i) {
-			printf("Fail to set rate to %dkhz", freq);
+			printf("Fail to set rate to %u kHz", freq);
 			return;
 		}
 	}
@@ -933,7 +937,7 @@ void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq)
 	}
 
 	if (best == 0) {
-		printf("Fail to set rate to %dkhz", freq);
+		printf("Fail to set rate to %u kHz", freq);
 		return;
 	}
 
@@ -1074,7 +1078,7 @@ void clock_init(void)
 	}
 }
 
-#ifdef CONFIG_SECURE_BOOT
+#ifdef CONFIG_IMX_HAB
 void hab_caam_clock_enable(unsigned char enable)
 {
 	if (enable)
@@ -1099,7 +1103,8 @@ void epdc_clock_disable(void)
 /*
  * Dump some core clockes.
  */
-int do_mx7_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_mx7_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
+		      char *const argv[])
 {
 	u32 freq;
 	freq = decode_pll(PLL_CORE, MXC_HCLK);
@@ -1111,17 +1116,17 @@ int do_mx7_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 	printf("\n");
 
-	printf("IPG        %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
-	printf("UART       %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
+	printf("IPG        %8u kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
+	printf("UART       %8u kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
 #ifdef CONFIG_MXC_SPI
-	printf("CSPI       %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
+	printf("CSPI       %8u kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
 #endif
-	printf("AHB        %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
-	printf("AXI        %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
-	printf("DDR        %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
-	printf("USDHC1     %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
-	printf("USDHC2     %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
-	printf("USDHC3     %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
+	printf("AHB        %8u kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
+	printf("AXI        %8u kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
+	printf("DDR        %8u kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
+	printf("USDHC1     %8u kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
+	printf("USDHC2     %8u kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
+	printf("USDHC3     %8u kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
 
 	return 0;
 }