X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=arch%2Farm%2Finclude%2Fasm%2Farch-sunxi%2Fclock_sun4i.h;h=58aff1687af357eca4439d1c55243def8cc8dc56;hb=d0f4200392515194bf67213165be906e5b9e5748;hp=70b789e8e8f7296030e0c2e8788d59e5c294e212;hpb=213480e12d880ef6782f56f1af95469b48cca539;p=platform%2Fkernel%2Fu-boot.git

diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
index 70b789e..58aff16 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
@@ -39,7 +39,7 @@ struct sunxi_ccm_reg {
 	u32 apb0_gate;		/* 0x68 apb0 module clock gating */
 	u32 apb1_gate;		/* 0x6c apb1 module clock gating */
 	u8 res4[0x10];
-	u32 nand_sclk_cfg;	/* 0x80 nand sub clock control */
+	u32 nand0_clk_cfg;	/* 0x80 nand sub clock control */
 	u32 ms_sclk_cfg;	/* 0x84 memory stick sub clock control */
 	u32 sd0_clk_cfg;	/* 0x88 sd0 clock control */
 	u32 sd1_clk_cfg;	/* 0x8c sd1 clock control */
@@ -144,7 +144,16 @@ struct sunxi_ccm_reg {
 
 #define PLL1_CFG_DEFAULT	0xa1005000
 
+#if defined CONFIG_OLD_SUNXI_KERNEL_COMPAT && defined CONFIG_MACH_SUN5I
+/*
+ * Older linux-sunxi-3.4 kernels override our PLL6 setting with 300 MHz,
+ * halving the mbus frequency, so set it to 300 MHz ourselves and base the
+ * mbus divider on that.
+ */
+#define PLL6_CFG_DEFAULT	0xa1009900
+#else
 #define PLL6_CFG_DEFAULT	0xa1009911
+#endif
 
 /* nand clock */
 #define NAND_CLK_SRC_OSC24		0
@@ -168,7 +177,7 @@ struct sunxi_ccm_reg {
 #define AHB_GATE_OFFSET_ACE		16
 #define AHB_GATE_OFFSET_DLL		15
 #define AHB_GATE_OFFSET_SDRAM		14
-#define AHB_GATE_OFFSET_NAND		13
+#define AHB_GATE_OFFSET_NAND0		13
 #define AHB_GATE_OFFSET_MS		12
 #define AHB_GATE_OFFSET_MMC3		11
 #define AHB_GATE_OFFSET_MMC2		10
@@ -182,10 +191,11 @@ struct sunxi_ccm_reg {
 #define AHB_GATE_OFFSET_USB_EHCI1	3
 #define AHB_GATE_OFFSET_USB_OHCI0	2
 #define AHB_GATE_OFFSET_USB_EHCI0	1
-#define AHB_GATE_OFFSET_USB		0
+#define AHB_GATE_OFFSET_USB0		0
 
 /* ahb clock gate bit offset (second register) */
 #define AHB_GATE_OFFSET_GMAC		17
+#define AHB_GATE_OFFSET_DE_FE0		14
 #define AHB_GATE_OFFSET_DE_BE0		12
 #define AHB_GATE_OFFSET_HDMI		11
 #define AHB_GATE_OFFSET_LCD1		5
@@ -266,7 +276,10 @@ struct sunxi_ccm_reg {
 #define CCM_MMC_CTRL_PLL5		(0x2 << 24)
 #define CCM_MMC_CTRL_ENABLE		(0x1 << 31)
 
+#define CCM_DRAM_GATE_OFFSET_DE_FE1	24 /* Note the order of FE1 and */
+#define CCM_DRAM_GATE_OFFSET_DE_FE0	25 /* FE0 is swapped ! */
 #define CCM_DRAM_GATE_OFFSET_DE_BE0	26
+#define CCM_DRAM_GATE_OFFSET_DE_BE1	27
 
 #define CCM_LCD_CH0_CTRL_PLL3		(0 << 24)
 #define CCM_LCD_CH0_CTRL_PLL7		(1 << 24)
@@ -301,11 +314,17 @@ struct sunxi_ccm_reg {
 #define CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII 0x2
 #define CCM_GMAC_CTRL_GPIT_MII (0x0 << 2)
 #define CCM_GMAC_CTRL_GPIT_RGMII (0x1 << 2)
+#define CCM_GMAC_CTRL_RX_CLK_DELAY(x)	((x) << 5)
+#define CCM_GMAC_CTRL_TX_CLK_DELAY(x)	((x) << 10)
 
+#define CCM_USB_CTRL_PHY0_RST (0x1 << 0)
 #define CCM_USB_CTRL_PHY1_RST (0x1 << 1)
 #define CCM_USB_CTRL_PHY2_RST (0x1 << 2)
+#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 6)
+#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 7)
 #define CCM_USB_CTRL_PHYGATE (0x1 << 8)
-/* These 2 are sun6i only, define them as 0 on sun4i */
+/* These 3 are sun6i only, define them as 0 on sun4i */
+#define CCM_USB_CTRL_PHY0_CLK 0
 #define CCM_USB_CTRL_PHY1_CLK 0
 #define CCM_USB_CTRL_PHY2_CLK 0
 
@@ -318,4 +337,11 @@ struct sunxi_ccm_reg {
 #define CCM_DE_CTRL_RST			(1 << 30)
 #define CCM_DE_CTRL_GATE		(1 << 31)
 
+#ifndef __ASSEMBLY__
+void clock_set_pll1(unsigned int hz);
+void clock_set_pll3(unsigned int hz);
+unsigned int clock_get_pll5p(void);
+unsigned int clock_get_pll6(void);
+#endif
+
 #endif /* _SUNXI_CLOCK_SUN4I_H */