X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=arch%2Farm%2Finclude%2Fasm%2Farch-rockchip%2Fclock.h;h=1d5b3a07d04b482153f11e4bcd76935303927646;hb=83d290c56fab2d38cd1ab4c4cc7099559c1d5046;hp=4bebd624798963172cb9672c11c2ef8f1649686e;hpb=b339b5dbca4c776a4c138b852082fad2df826410;p=platform%2Fkernel%2Fu-boot.git diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h index 4bebd62..1d5b3a0 100644 --- a/arch/arm/include/asm/arch-rockchip/clock.h +++ b/arch/arm/include/asm/arch-rockchip/clock.h @@ -1,7 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* * (C) Copyright 2015 Google, Inc - * - * SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_ARCH_CLOCK_H @@ -16,6 +15,10 @@ enum { ROCKCHIP_SYSCON_GRF, ROCKCHIP_SYSCON_SGRF, ROCKCHIP_SYSCON_PMU, + ROCKCHIP_SYSCON_PMUGRF, + ROCKCHIP_SYSCON_PMUSGRF, + ROCKCHIP_SYSCON_CIC, + ROCKCHIP_SYSCON_MSCH, }; /* Standard Rockchip clock numbers */ @@ -35,6 +38,11 @@ static inline int rk_pll_id(enum rk_clk_id clk_id) return clk_id - 1; } +struct sysreset_reg { + unsigned int glb_srst_fst_value; + unsigned int glb_srst_snd_value; +}; + /** * clk_get_divisor() - Calculate the required clock divisior * @@ -62,9 +70,28 @@ static inline u32 clk_get_divisor(ulong input_rate, uint output_rate) */ void *rockchip_get_cru(void); +/** + * rockchip_get_pmucru() - get a pointer to the clock/reset unit registers + * + * @return pointer to registers, or -ve error on error + */ +void *rockchip_get_pmucru(void); + struct rk3288_cru; struct rk3288_grf; void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf); +int rockchip_get_clk(struct udevice **devp); + +/* + * rockchip_reset_bind() - Bind soft reset device as child of clock device + * + * @pdev: clock udevice + * @reg_offset: the first offset in cru for softreset registers + * @reg_number: the reg numbers of softreset registers + * @return 0 success, or error value + */ +int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number); + #endif