X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=arch%2Farm%2Finclude%2Fasm%2Farch-omap5%2Fomap.h;h=4fcd99f9925e2eee15540a3d1852540328caef12;hb=9239f5b62550e9f1438c784cb8d1e578dc3852a8;hp=1c1a64bd234e95a2b7393327da360d3c37dd2da1;hpb=e0a8c99e6103a9052510ea9e2067c18cb688e1cb;p=platform%2Fkernel%2Fu-boot.git

diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
index 1c1a64b..4fcd99f 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -44,16 +44,8 @@
 #define DRAM_ADDR_SPACE_START	OMAP54XX_DRAM_ADDR_SPACE_START
 #define DRAM_ADDR_SPACE_END	OMAP54XX_DRAM_ADDR_SPACE_END
 
-/* CONTROL */
-#define CTRL_BASE		(OMAP54XX_L4_CORE_BASE + 0x2000)
-#define CONTROL_PADCONF_CORE	(CTRL_BASE + 0x0800)
-#define CONTROL_PADCONF_WKUP	(OMAP54XX_L4_WKUP_BASE + 0xc800)
-
-/* LPDDR2 IO regs. To be verified */
-#define LPDDR2_IO_REGS_BASE	0x4A100638
-
 /* CONTROL_ID_CODE */
-#define CONTROL_ID_CODE		(CTRL_BASE + 0x204)
+#define CONTROL_ID_CODE		0x4A002204
 
 /* To be verified */
 #define OMAP5430_CONTROL_ID_CODE_ES1_0		0x0B94202F
@@ -62,11 +54,6 @@
 #define OMAP5432_CONTROL_ID_CODE_ES2_0          0x1B99802F
 #define DRA752_CONTROL_ID_CODE_ES1_0		0x0B99002F
 
-/* STD_FUSE_PROD_ID_1 */
-#define STD_FUSE_PROD_ID_1		(CTRL_BASE + 0x218)
-#define PROD_ID_1_SILICON_TYPE_SHIFT	16
-#define PROD_ID_1_SILICON_TYPE_MASK	(3 << 16)
-
 /* UART */
 #define UART1_BASE		(OMAP54XX_L4_PER_BASE + 0x6a000)
 #define UART2_BASE		(OMAP54XX_L4_PER_BASE + 0x6c000)
@@ -80,15 +67,9 @@
 /* Watchdog Timer2 - MPU watchdog */
 #define WDT2_BASE		(OMAP54XX_L4_WKUP_BASE + 0x14000)
 
-/* 32KTIMER */
-#define SYNC_32KTIMER_BASE	(OMAP54XX_L4_WKUP_BASE + 0x4000)
-
 /* GPMC */
 #define OMAP54XX_GPMC_BASE	0x50000000
 
-/* SYSTEM CONTROL MODULE */
-#define SYSCTRL_GENERAL_CORE_BASE	0x4A002000
-
 /*
  * Hardware Register Details
  */
@@ -191,16 +172,6 @@ struct s32ktimer {
 /* base address for indirect vectors (internal boot mode) */
 #define SRAM_ROM_VECT_BASE	0x4031F000
 
-/* Silicon revisions */
-#define OMAP4430_SILICON_ID_INVALID	0xFFFFFFFF
-#define OMAP4430_ES1_0	0x44300100
-#define OMAP4430_ES2_0	0x44300200
-#define OMAP4430_ES2_1	0x44300210
-#define OMAP4430_ES2_2	0x44300220
-#define OMAP4430_ES2_3	0x44300230
-#define OMAP4460_ES1_0	0x44600100
-#define OMAP4460_ES1_1	0x44600110
-
 /* CONTROL_SRCOMP_XXX_SIDE */
 #define OVERRIDE_XS_SHIFT		30
 #define OVERRIDE_XS_MASK		(1 << 30)