X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=arch%2Farm%2Finclude%2Fasm%2Farch-omap5%2Fcpu.h;h=9e5655319c5955f8046591e2ba85c734e9d4c32a;hb=83d290c56fab2d38cd1ab4c4cc7099559c1d5046;hp=8ef17c9a146aab0368f914b133621445c0accd66;hpb=d417d1db5f9092d125ddea882ced77eaa5f3d236;p=platform%2Fkernel%2Fu-boot.git

diff --git a/arch/arm/include/asm/arch-omap5/cpu.h b/arch/arm/include/asm/arch-omap5/cpu.h
index 8ef17c9..9e56553 100644
--- a/arch/arm/include/asm/arch-omap5/cpu.h
+++ b/arch/arm/include/asm/arch-omap5/cpu.h
@@ -1,27 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * (C) Copyright 2006-2010
  * Texas Instruments, <www.ti.com>
  *
  *	Aneesh V <aneesh@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
  */
 
 #ifndef _CPU_H
@@ -31,52 +13,11 @@
 #include <asm/types.h>
 #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
 
+#include <asm/arch/hardware.h>
+
 #ifndef __KERNEL_STRICT_NAMES
 #ifndef __ASSEMBLY__
-struct gpmc_cs {
-	u32 config1;		/* 0x00 */
-	u32 config2;		/* 0x04 */
-	u32 config3;		/* 0x08 */
-	u32 config4;		/* 0x0C */
-	u32 config5;		/* 0x10 */
-	u32 config6;		/* 0x14 */
-	u32 config7;		/* 0x18 */
-	u32 nand_cmd;		/* 0x1C */
-	u32 nand_adr;		/* 0x20 */
-	u32 nand_dat;		/* 0x24 */
-	u8 res[8];		/* blow up to 0x30 byte */
-};
-
-struct gpmc {
-	u8 res1[0x10];
-	u32 sysconfig;		/* 0x10 */
-	u8 res2[0x4];
-	u32 irqstatus;		/* 0x18 */
-	u32 irqenable;		/* 0x1C */
-	u8 res3[0x20];
-	u32 timeout_control;	/* 0x40 */
-	u8 res4[0xC];
-	u32 config;		/* 0x50 */
-	u32 status;		/* 0x54 */
-	u8 res5[0x8];	/* 0x58 */
-	struct gpmc_cs cs[8];	/* 0x60, 0x90, .. */
-	u8 res6[0x14];		/* 0x1E0 */
-	u32 ecc_config;		/* 0x1F4 */
-	u32 ecc_control;	/* 0x1F8 */
-	u32 ecc_size_config;	/* 0x1FC */
-	u32 ecc1_result;	/* 0x200 */
-	u32 ecc2_result;	/* 0x204 */
-	u32 ecc3_result;	/* 0x208 */
-	u32 ecc4_result;	/* 0x20C */
-	u32 ecc5_result;	/* 0x210 */
-	u32 ecc6_result;	/* 0x214 */
-	u32 ecc7_result;	/* 0x218 */
-	u32 ecc8_result;	/* 0x21C */
-	u32 ecc9_result;	/* 0x220 */
-};
-
-/* Used for board specific gpmc initialization */
-extern struct gpmc *gpmc_cfg;
+#include <asm/ti-common/omap_wdt.h>
 
 struct gptimer {
 	u32 tidr;		/* 0x00 r */
@@ -104,6 +45,7 @@ struct gptimer {
 /* enable sys_clk NO-prescale /1 */
 #define GPT_EN			((0x0 << 2) | (0x1 << 1) | (0x1 << 0))
 
+#define WDT_BASE                (OMAP54XX_L4_WKUP_BASE + 0x14000)
 /* Watchdog */
 #ifndef __KERNEL_STRICT_NAMES
 #ifndef __ASSEMBLY__
@@ -119,29 +61,16 @@ struct watchdog {
 #define WD_UNLOCK1		0xAAAA
 #define WD_UNLOCK2		0x5555
 
-#define SYSCLKDIV_1		(0x1 << 6)
-#define SYSCLKDIV_2		(0x1 << 7)
-
-#define CLKSEL_GPT1		(0x1 << 0)
-
-#define EN_GPT1			(0x1 << 0)
-#define EN_32KSYNC		(0x1 << 2)
-
-#define ST_WDT2			(0x1 << 5)
-
-#define RESETDONE		(0x1 << 0)
-
 #define TCLR_ST			(0x1 << 0)
 #define TCLR_AR			(0x1 << 1)
 #define TCLR_PRE		(0x1 << 5)
 
-/* GPMC BASE */
-#define GPMC_BASE		(OMAP54XX_GPMC_BASE)
-
 /* I2C base */
 #define I2C_BASE1		(OMAP54XX_L4_PER_BASE + 0x70000)
 #define I2C_BASE2		(OMAP54XX_L4_PER_BASE + 0x72000)
 #define I2C_BASE3		(OMAP54XX_L4_PER_BASE + 0x60000)
+#define I2C_BASE4		(OMAP54XX_L4_PER_BASE + 0x7A000)
+#define I2C_BASE5		(OMAP54XX_L4_PER_BASE + 0x7C000)
 
 /* MUSB base */
 #define MUSB_BASE		(OMAP54XX_L4_CORE_BASE + 0xAB000)
@@ -182,5 +111,23 @@ struct watchdog {
 
 #define PRM_RSTCTRL		PRM_DEVICE_BASE
 #define PRM_RSTCTRL_RESET	0x01
+#define PRM_RSTST		(PRM_DEVICE_BASE + 0x4)
+#define PRM_RSTST_WARM_RESET_MASK	0x7FEA
+
+/* DRA7XX CPSW Config space */
+#define CPSW_BASE			0x48484000
+#define CPSW_MDIO_BASE			0x48485000
+
+/* gmii_sel register defines */
+#define GMII1_SEL_MII		0x0
+#define GMII1_SEL_RMII		0x1
+#define GMII1_SEL_RGMII		0x2
+#define GMII2_SEL_MII		(GMII1_SEL_MII << 4)
+#define GMII2_SEL_RMII		(GMII1_SEL_RMII << 4)
+#define GMII2_SEL_RGMII		(GMII1_SEL_RGMII << 4)
+
+#define MII_MODE_ENABLE		(GMII1_SEL_MII | GMII2_SEL_MII)
+#define RMII_MODE_ENABLE        (GMII1_SEL_RMII | GMII2_SEL_RMII)
+#define RGMII_MODE_ENABLE	(GMII1_SEL_RGMII | GMII2_SEL_RGMII)
 
 #endif /* _CPU_H */