X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=arch%2Farm%2Finclude%2Fasm%2Farch-mx5%2Fimx-regs.h;h=054c680a5a14ec40304aef6876d72fd8081ac16d;hb=1ad6364eeb4f578e423081d1748e8a3fdf1ab01d;hp=0ee88d25b7800ae9e6aed809d02dd19d9cac9c82;hpb=40f6fffee5917930597bfcc07de1cd879d4994f6;p=platform%2Fkernel%2Fu-boot.git diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h index 0ee88d2..054c680 100644 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -1,31 +1,18 @@ /* * (C) Copyright 2009 Freescale Semiconductor, Inc. * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __ASM_ARCH_MX5_IMX_REGS_H__ #define __ASM_ARCH_MX5_IMX_REGS_H__ +#define ARCH_MXC + #if defined(CONFIG_MX51) #define IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */ -#define IPU_CTRL_BASE_ADDR 0x40000000 +#define IPU_SOC_BASE_ADDR 0x40000000 +#define IPU_SOC_OFFSET 0x1E000000 #define SPBA0_BASE_ADDR 0x70000000 #define AIPS1_BASE_ADDR 0x73F00000 #define AIPS2_BASE_ADDR 0x83F00000 @@ -34,7 +21,8 @@ #define NFC_BASE_ADDR_AXI 0xCFFF0000 #define CS1_BASE_ADDR 0xB8000000 #elif defined(CONFIG_MX53) -#define IPU_CTRL_BASE_ADDR 0x18000000 +#define IPU_SOC_BASE_ADDR 0x18000000 +#define IPU_SOC_OFFSET 0x06000000 #define SPBA0_BASE_ADDR 0x50000000 #define AIPS1_BASE_ADDR 0x53F00000 #define AIPS2_BASE_ADDR 0x63F00000 @@ -43,6 +31,7 @@ #define NFC_BASE_ADDR_AXI 0xF7FF0000 #define IRAM_BASE_ADDR 0xF8000000 #define CS1_BASE_ADDR 0xF4000000 +#define SATA_BASE_ADDR 0x10000000 #else #error "CPU_TYPE not defined" #endif @@ -93,6 +82,8 @@ #define GPIO5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000DC000) #define GPIO6_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E0000) #define GPIO7_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E4000) +#define I2C3_BASE_ADDR (AIPS1_BASE_ADDR + 0x000EC000) +#define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000F0000) #endif /* * AIPS 2 @@ -133,6 +124,10 @@ #define VPU_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F4000) #define SAHARA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F8000) +#if defined(CONFIG_MX53) +#define UART5_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000) +#endif + /* * WEIM CSnGCR1 */ @@ -207,22 +202,44 @@ */ #define WBED 1 -/* - * WEIM WCR - */ -#define BCM 1 -#define GBCD(x) (((x) & 0x3) << 1) -#define INTEN (1 << 4) -#define INTPOL (1 << 5) -#define WDOG_EN (1 << 8) -#define WDOG_LIMIT(x) (((x) & 0x3) << 9) - #define CS0_128 0 #define CS0_64M_CS1_64M 1 #define CS0_64M_CS1_32M_CS2_32M 2 #define CS0_32M_CS1_32M_CS2_32M_CS3_32M 3 /* + * CSPI register definitions + */ +#define MXC_ECSPI +#define MXC_CSPICTRL_EN (1 << 0) +#define MXC_CSPICTRL_MODE (1 << 1) +#define MXC_CSPICTRL_XCH (1 << 2) +#define MXC_CSPICTRL_MODE_MASK (0xf << 4) +#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) +#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) +#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12) +#define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8) +#define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18) +#define MXC_CSPICTRL_MAXBITS 0xfff +#define MXC_CSPICTRL_TC (1 << 7) +#define MXC_CSPICTRL_RXOVF (1 << 6) +#define MXC_CSPIPERIOD_32KHZ (1 << 15) +#define MAX_SPI_BYTES 32 + +/* Bit position inside CTRL register to be associated with SS */ +#define MXC_CSPICTRL_CHAN 18 + +/* Bit position inside CON register to be associated with SS */ +#define MXC_CSPICON_PHA 0 /* SCLK phase control */ +#define MXC_CSPICON_POL 4 /* SCLK polarity */ +#define MXC_CSPICON_SSPOL 12 /* SS polarity */ +#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */ +#define MXC_SPI_BASE_ADDRESSES \ + CSPI1_BASE_ADDR, \ + CSPI2_BASE_ADDR, \ + CSPI3_BASE_ADDR, + +/* * Number of GPIO pins per port */ #define GPIO_NUM_PIN 32 @@ -235,6 +252,8 @@ /* M4IF */ #define M4IF_FBPM0 0x40 #define M4IF_FIDBP 0x48 +#define M4IF_GENP_WEIM_MM_MASK 0x00000001 +#define WEIM_GCR2_MUX16_BYP_GRANT_MASK 0x00001000 /* Assuming 24MHz input clock with doubler ON */ /* MFI PDF */ @@ -267,6 +286,10 @@ #define DP_MFD_400 (3 - 1) #define DP_MFN_400 1 +#define DP_OP_455 ((9 << 4) + ((2 - 1) << 0)) +#define DP_MFD_455 (48 - 1) +#define DP_MFN_455 23 + #define DP_OP_216 ((6 << 4) + ((3 - 1) << 0)) #define DP_MFD_216 (4 - 1) #define DP_MFN_216 3 @@ -280,6 +303,8 @@ #define BOARD_REV_1_0 0x0 #define BOARD_REV_2_0 0x1 +#define BOARD_VER_OFFSET 0x8 + #define IMX_IIM_BASE (IIM_BASE_ADDR) #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) @@ -420,6 +445,24 @@ struct src { u32 simr; }; +struct srtc_regs { + u32 lpscmr; /* 0x00 */ + u32 lpsclr; /* 0x04 */ + u32 lpsar; /* 0x08 */ + u32 lpsmcr; /* 0x0c */ + u32 lpcr; /* 0x10 */ + u32 lpsr; /* 0x14 */ + u32 lppdr; /* 0x18 */ + u32 lpgr; /* 0x1c */ + u32 hpcmr; /* 0x20 */ + u32 hpclr; /* 0x24 */ + u32 hpamr; /* 0x28 */ + u32 hpalr; /* 0x2c */ + u32 hpcr; /* 0x30 */ + u32 hpisr; /* 0x34 */ + u32 hpienr; /* 0x38 */ +}; + /* CSPI registers */ struct cspi_regs { u32 rxdata; @@ -443,7 +486,7 @@ struct iim_regs { u32 sdat; u32 prev; u32 srev; - u32 preg_p; + u32 prg_p; u32 scs0; u32 scs1; u32 scs2; @@ -452,7 +495,22 @@ struct iim_regs { struct fuse_bank { u32 fuse_regs[0x20]; u32 fuse_rsvd[0xe0]; +#if defined(CONFIG_MX51) } bank[4]; +#elif defined(CONFIG_MX53) + } bank[5]; +#endif +}; + +struct fuse_bank0_regs { + u32 fuse0_7[8]; + u32 uid[8]; + u32 fuse16_23[8]; +#if defined(CONFIG_MX51) + u32 imei[8]; +#elif defined(CONFIG_MX53) + u32 gp[8]; +#endif }; struct fuse_bank1_regs { @@ -461,6 +519,14 @@ struct fuse_bank1_regs { u32 fuse15_31[0x11]; }; +#if defined(CONFIG_MX53) +struct fuse_bank4_regs { + u32 fuse0_4[5]; + u32 gp[3]; + u32 fuse8_31[0x18]; +}; +#endif + #endif /* __ASSEMBLER__*/ #endif /* __ASM_ARCH_MX5_IMX_REGS_H__ */