X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=arch%2Farm%2Finclude%2Fasm%2Farch-fsl-layerscape%2Fimmap_lsch3.h;h=863618a5f3d0a65a00eeb96946b5cb5f9e9b4f88;hb=87a9aa604de8a4a50642e25b88af328ab375893b;hp=baa9fa8529cdb915696103bb4d75649f3d792529;hpb=c27178ba3649f539c9f1890ea147f4c5415f63b5;p=platform%2Fkernel%2Fu-boot.git

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index baa9fa8..863618a 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -2,20 +2,19 @@
 /*
  * LayerScape Internal Memory Map
  *
- * Copyright 2017-2019 NXP
+ * Copyright 2017-2020 NXP
  * Copyright 2014 Freescale Semiconductor, Inc.
  */
 
 #ifndef __ARCH_FSL_LSCH3_IMMAP_H_
 #define __ARCH_FSL_LSCH3_IMMAP_H_
 
-#define CONFIG_SYS_IMMR				0x01000000
 #define CONFIG_SYS_FSL_DDR_ADDR			(CONFIG_SYS_IMMR + 0x00080000)
 #define CONFIG_SYS_FSL_DDR2_ADDR		(CONFIG_SYS_IMMR + 0x00090000)
 #define CONFIG_SYS_FSL_DDR3_ADDR		0x08210000
 #define CONFIG_SYS_FSL_GUTS_ADDR		(CONFIG_SYS_IMMR + 0x00E00000)
 #define CONFIG_SYS_FSL_PMU_ADDR			(CONFIG_SYS_IMMR + 0x00E30000)
-#ifdef CONFIG_ARCH_LX2160A
+#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
 #define CONFIG_SYS_FSL_RST_ADDR			(CONFIG_SYS_IMMR + 0x00e88180)
 #else
 #define CONFIG_SYS_FSL_RST_ADDR			(CONFIG_SYS_IMMR + 0x00E60000)
@@ -198,12 +197,12 @@
 #define CONFIG_SYS_PCIE2_ADDR			(CONFIG_SYS_IMMR + 0x2500000)
 #define CONFIG_SYS_PCIE3_ADDR			(CONFIG_SYS_IMMR + 0x2600000)
 #define CONFIG_SYS_PCIE4_ADDR			(CONFIG_SYS_IMMR + 0x2700000)
-#ifdef CONFIG_ARCH_LX2160A
+#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
 #define SYS_PCIE5_ADDR				(CONFIG_SYS_IMMR + 0x2800000)
 #define SYS_PCIE6_ADDR				(CONFIG_SYS_IMMR + 0x2900000)
 #endif
 
-#ifdef CONFIG_ARCH_LX2160A
+#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
 #define CONFIG_SYS_PCIE1_PHYS_ADDR		0x8000000000ULL
 #define CONFIG_SYS_PCIE2_PHYS_ADDR		0x8800000000ULL
 #define CONFIG_SYS_PCIE3_PHYS_ADDR		0x9000000000ULL
@@ -267,7 +266,7 @@
 	defined(CONFIG_ARCH_LS1028A)
 #define USB_PHY_RX_EQ_VAL_3		0x0380
 #define USB_PHY_RX_EQ_VAL_4		0x0b80
-#elif defined(CONFIG_ARCH_LX2160A)
+#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
 #define USB_PHY_RX_EQ_VAL_3		0x0080
 #define USB_PHY_RX_EQ_VAL_4		0x0880
 #endif
@@ -391,12 +390,12 @@ struct ccsr_gur {
 #define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT	FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT
 #define FSL_CHASSIS3_SRDS1_REGSR	29
 #define FSL_CHASSIS3_SRDS2_REGSR	29
-#elif defined(CONFIG_ARCH_LX2160A)
+#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
 #define FSL_CHASSIS3_EC1_REGSR  27
 #define FSL_CHASSIS3_EC2_REGSR  27
 #define FSL_CHASSIS3_EC1_REGSR_PRTCL_MASK	0x00000003
 #define FSL_CHASSIS3_EC1_REGSR_PRTCL_SHIFT	0
-#define FSL_CHASSIS3_EC2_REGSR_PRTCL_MASK	0x00000007
+#define FSL_CHASSIS3_EC2_REGSR_PRTCL_MASK	0x0000000C
 #define FSL_CHASSIS3_EC2_REGSR_PRTCL_SHIFT	2
 #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK   0x001F0000
 #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT  16
@@ -589,5 +588,15 @@ struct ccsr_serdes {
 	u8 res5[0x19fc - 0xa00];
 };
 
+struct ccsr_gpio {
+	u32	gpdir;
+	u32	gpodr;
+	u32	gpdat;
+	u32	gpier;
+	u32	gpimr;
+	u32	gpicr;
+	u32	gpibe;
+};
+
 #endif /*__ASSEMBLY__ */
 #endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */