X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=arch%2Farm%2Finclude%2Fasm%2Farch-fsl-layerscape%2Fcpu.h;h=c4e5eccd77b5c3e1107b0ca2b714ef5353fe47ab;hb=235c5b8315c6a9eb566fd3d99a098cc6db869fc5;hp=bcf3e3863e6f08e1dc39b1e4dc3f8ec1fff61fa2;hpb=f9515756b6d76cde99b385dda905dfb20d31ea48;p=platform%2Fkernel%2Fu-boot.git

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index bcf3e38..c4e5ecc 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -1,4 +1,5 @@
 /*
+ * Copyright 2017 NXP
  * Copyright 2014-2015, Freescale Semiconductor
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -15,6 +16,8 @@ static struct cpu_type cpu_type_list[] = {
 	CPU_TYPE_ENTRY(LS2084A, LS2084A, 8),
 	CPU_TYPE_ENTRY(LS2048A, LS2048A, 4),
 	CPU_TYPE_ENTRY(LS2044A, LS2044A, 4),
+	CPU_TYPE_ENTRY(LS2081A, LS2081A, 8),
+	CPU_TYPE_ENTRY(LS2041A, LS2041A, 4),
 	CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
 	CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
 	CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),
@@ -249,7 +252,7 @@ static struct mm_region final_map[] = {
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
-#ifdef CONFIG_LS2080A
+#ifdef CONFIG_ARCH_LS2080A
 	{ CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
 	  CONFIG_SYS_PCIE4_PHYS_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
@@ -350,4 +353,5 @@ static struct mm_region final_map[] = {
 
 int fsl_qoriq_core_to_cluster(unsigned int core);
 u32 cpu_mask(void);
+
 #endif /* _FSL_LAYERSCAPE_CPU_H */