X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=arch%2Farm%2Finclude%2Fasm%2Farch-am33xx%2Fddr_defs.h;h=d2f3a78a17c86697e3602b6cd237cac909118c30;hb=fbbbc86e8ebac4f42f4ca39ceba80cea27c983bc;hp=260cc3484f09330fdcb19707a1db89c1f3058c8d;hpb=009d75ccc11d27b9a083375a88bb93cb746b4800;p=platform%2Fkernel%2Fu-boot.git

diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index 260cc34..d2f3a78 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -84,20 +84,20 @@
 #define MT41J256M8HX15E_IOCTRL_VALUE		0x18B
 
 /* Micron MT41K256M16HA-125E */
-#define MT41K256M16HA125E_EMIF_READ_LATENCY	0x100006
-#define MT41K256M16HA125E_EMIF_TIM1		0x0888A39B
-#define MT41K256M16HA125E_EMIF_TIM2		0x26517FDA
-#define MT41K256M16HA125E_EMIF_TIM3		0x501F84EF
-#define MT41K256M16HA125E_EMIF_SDCFG		0x61C04BB2
-#define MT41K256M16HA125E_EMIF_SDREF		0x0000093B
+#define MT41K256M16HA125E_EMIF_READ_LATENCY	0x100007
+#define MT41K256M16HA125E_EMIF_TIM1		0x0AAAD4DB
+#define MT41K256M16HA125E_EMIF_TIM2		0x266B7FDA
+#define MT41K256M16HA125E_EMIF_TIM3		0x501F867F
+#define MT41K256M16HA125E_EMIF_SDCFG		0x61C05332
+#define MT41K256M16HA125E_EMIF_SDREF		0xC30
 #define MT41K256M16HA125E_ZQ_CFG		0x50074BE4
 #define MT41K256M16HA125E_DLL_LOCK_DIFF		0x1
-#define MT41K256M16HA125E_RATIO			0x40
+#define MT41K256M16HA125E_RATIO			0x80
 #define MT41K256M16HA125E_INVERT_CLKOUT		0x0
-#define MT41K256M16HA125E_RD_DQS		0x3C
-#define MT41K256M16HA125E_WR_DQS		0x45
-#define MT41K256M16HA125E_PHY_WR_DATA		0x7F
-#define MT41K256M16HA125E_PHY_FIFO_WE		0x9B
+#define MT41K256M16HA125E_RD_DQS		0x38
+#define MT41K256M16HA125E_WR_DQS		0x44
+#define MT41K256M16HA125E_PHY_WR_DATA		0x7D
+#define MT41K256M16HA125E_PHY_FIFO_WE		0x94
 #define MT41K256M16HA125E_IOCTRL_VALUE		0x18B
 
 /* Micron MT41J512M8RH-125 on EVM v1.5 */
@@ -117,6 +117,23 @@
 #define MT41J512M8RH125_PHY_WR_DATA		0x74
 #define MT41J512M8RH125_IOCTRL_VALUE		0x18B
 
+/* Samsung K4B2G1646E-BIH9 */
+#define K4B2G1646EBIH9_EMIF_READ_LATENCY	0x06
+#define K4B2G1646EBIH9_EMIF_TIM1		0x0888A39B
+#define K4B2G1646EBIH9_EMIF_TIM2		0x2A04011A
+#define K4B2G1646EBIH9_EMIF_TIM3		0x501F820F
+#define K4B2G1646EBIH9_EMIF_SDCFG		0x61C24AB2
+#define K4B2G1646EBIH9_EMIF_SDREF		0x0000093B
+#define K4B2G1646EBIH9_ZQ_CFG			0x50074BE4
+#define K4B2G1646EBIH9_DLL_LOCK_DIFF		0x1
+#define K4B2G1646EBIH9_RATIO			0x40
+#define K4B2G1646EBIH9_INVERT_CLKOUT		0x1
+#define K4B2G1646EBIH9_RD_DQS			0x3B
+#define K4B2G1646EBIH9_WR_DQS			0x85
+#define K4B2G1646EBIH9_PHY_FIFO_WE		0x100
+#define K4B2G1646EBIH9_PHY_WR_DATA		0xC1
+#define K4B2G1646EBIH9_IOCTRL_VALUE		0x18B
+
 /**
  * Configure DMM
  */
@@ -267,7 +284,6 @@ void config_ddr_data(const struct ddr_data *data, int nr);
  * This structure represents the DDR io control on AM33XX devices.
  */
 struct ddr_cmdtctrl {
-	unsigned int resv1[1];
 	unsigned int cm0ioctl;
 	unsigned int cm1ioctl;
 	unsigned int cm2ioctl;